GS8150V18AB Просмотр технического описания (PDF) - Giga Semiconductor
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GS8150V18AB Datasheet PDF : 25 Pages
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GS8150V18/36AB-357/333/300/250
Write Operations
Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge
of the K clock (and falling edge of the K clock).
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control
inputs are captured by the same clock edge used to capture SW.
Example of x36 Byte Write Truth Table
Function
SW
Ba
Bb
Bc
Bd
Read
H
X
X
X
X
Write Byte A
L
L
H
H
H
Write Byte B
L
H
L
H
H
Write Byte C
L
H
H
L
H
Write Byte D
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort
L
H
H
H
H
FLXDrive-II™ HSTL Output Driver Impedance Control
HSTL I/O SigmaRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an
external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value
of the desired SRAM driver impedance. The allowable range of RQ to guarantee impedance matching with specified tolerance is
between 150Ω and 300Ω. Periodic readjustment of the output driver impedance occurs automatically because driver impedance is
affected by drifts in supply voltage and die temperature. A clock cycle counter periodically triggers an impedance evaluation,
resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the
optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires 32K start-up
clock cycles, selected or deselected, after VDD reaches its operating range to reach its programmed output driver impedance.
Rev: 1.04 4/2005
5/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
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