GS7005-CTT Просмотр технического описания (PDF) - Gennum -> Semtech

Номер в каталоге

Компоненты Описание

производитель

GS7005-CTT

Complete Serial Digital Video Receiver

Gennum -> Semtech 

RECEIVER OPERATION

EQ

SMPTE

GS7005 Operating mode

0

0

SMPTE 259M Receiver (Equalizer ON, SMPTE / NRZI Descrambler enabled).

1

0

SMPTE 259M Receiver with equalizer bypassed.

0

1

Receiver function with equalizer enabled and NRZI and SMPTE Descrambler disabled.

1

1

Receiver function with equalizer bypassed and NRZI and SMPTE Descrambler disabled.

The output of the LOCK pin is logic high approximately

38µs after the receiver has successfully locked to the input

serial bit stream. The output H is set low after the SAV ID

and is set high after the EAV ID when these sequences are

identified in the incoming bit stream.

If external equalization is performed prior to this device,

bypass the equalization control function (EQ) by setting it

HIGH.

To turn off the NRZI and SMPTE Descrambler function, set

SMPTE HIGH. When operating in this mode, the output of H

is either "1" or "0" (indeterminate).

DIAGRAMS

The figure below shows the timing relationship between the outputs of the GS7005.

PCLKOUT

...

DOUT[9:0] XXX XXX 3FF 000 000 SAV ID XXX XXX XXX XXX ... XXX XXX 3FF 000 000 EAV ID XXX XXX

H

...

Fig. 9 Timing Diagram for Parallel Outputs, PCLKOUT, and H

The figure below shows the relationship between the parallel clock and the parallel data outputs. The rising edge of the

parallel clock is within ±5ns of the centre of the data.

WORD CENTRE

5ns

5ns

DOUT[9:0]

PCLKOUT

Fig. 10 Parallel Clock Alignment

8

GENNUM CORPORATION

522 - 14 - 07

Share Link: