LCX028ALT Просмотр технического описания (PDF) - Sony Semiconductor
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LCX028ALT Datasheet PDF : 25 Pages
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LCX028ALT
2. Clock timing conditions (Ta = 25°C)
(SXGA mode: fHckn = 4.5MHz, fVck = 32.0kHz, fv = 60Hz)
Item
Symbol Min.
Typ.
Max. Unit
HST
HCK
Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn rise time∗5
Hckn fall time∗5
Hck1 fall to Hck2 rise time
trHst
—
—
tfHst
—
—
tdHst
35
45
thHst
35
45
trHckn
—
—
tfHckn
—
—
to1Hck
–15
0
30
30
55
55
30
ns
30
15
Hck1 rise to Hck2 fall time
Vst rise time
to2Hck
–15
0
15
trVst
—
—
100
Vst fall time
VST
Vst data set-up time
Vst data hold time
tfVst
—
—
100
tdVst
2
thVst
2
6
10
µs
6
10
Vck rise time
VCK
Vck fall time
trVck
—
—
100
tfVck
—
—
100
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Horizontal video period completed to Enb fall time tdEnb
450∗6
700
—
ENB
Enb rise to horizontal video period started
toPRG∗4 800
1100
—
Enb fall to Pcg rise time
toPcg
750
1000
—
Enb pulse width
twEnb
1800
—
—
PCG
Pcg rise time
Pcg fall time
Pcg rise to Vck rise/fall time
trPcg
—
—
tfPcg
—
—
toVck
–100
0
30
ns
30
100
Pcg fall to horizontal video period start time
toVideo 200
270
—
Pcg pulse width
PRG∗4 rise to Pcg rise time
PRG∗4 PRG∗4 fall to Pcg fall time
PRG∗4 pulse width
twPcg
1600
1800
—
toPcgr
–10
0
10
toPcgf
400
600
—
twPRG∗4 1100
1200
—
Blk rise time
trBlk
—
—
100
Blk fall time
BLK∗5
Blk rise to Enb fall time
Blk fall to Pcg rise time
tfBlk
—
toEnb
2
toPcg
–1
—
100
1
0
µs
0
1
∗5 Hckn means Hck1 and Hck2.
∗6 The minimum value of tdEnb is 450ns. When H-BLK has a long cycle and has some time to spare, take
more time prior to other value.
∗7 Blk is the timing during 4:3 and 16:9 aspect-ratio mode, which keeps "H" level in other modes.
–7–
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