GAL18V10 Просмотр технического описания (PDF) - Lattice Semiconductor

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GAL18V10

High Performance E2CMOS PLD Generic Array Logic™

Lattice Semiconductor 

fmax Descriptions

CLK

LOGIC

ARRAY

REGISTER

tsu

tco

fmax with External Feedback 1/(tsu+tco)

Note: fmax with external feedback is cal-

culated from measured tsu and tco.

CLK

LOGIC

ARRAY

REGISTER

tsu + th

fmax with No Feedback

Note: fmax with no feedback may be less

than 1/(twh + twl). This is to allow for a

clock duty cycle of other than 50%.

Switching Test Conditions

Input Pulse Levels

Input Rise and

-7/-10

Fall Times

-15/-20

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

2ns 10% – 90%

3ns 10% – 90%

1.5V

1.5V

See Figure

3-state levels are measured 0.5V from steady-state active

level.

Output Load Conditions (see figure)

Test Condition

R1

R2

CL

A

B Active High

Active Low

C Active High

Active Low

300Ω

∞

300Ω

∞

300Ω

390Ω

390Ω

390Ω

390Ω

390Ω

50pF

50pF

50pF

5pF

5pF

Specifications GAL18V10

LOGIC

ARRAY

CLK

REGISTER

t cf

t pd

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by sub-

tracting tsu from the period of fmax w/internal

feedback (tcf = 1/fmax - tsu). The value of tcf is

used primarily when calculating the delay from

clocking a register to a combinatorial output

(through registered feedback), as shown above.

For example, the timing from clock to a combi-

natorial output is equal to tcf + tpd.

+5V

R1

FROM OUTPUT (O/Q)

UNDER TEST

R2

TEST POINT

C L*

*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

9

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