GAL18V10 Просмотр технического описания (PDF) - Lattice Semiconductor
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GAL18V10 Datasheet PDF : 14 Pages
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Specifications GAL18V10
GAL18V10 Logic Diagram/JEDEC Fuse Map
DIP and PLCC Package Pinouts
1
0
4
8
12
16
20
24
28
32
0000
0036
.
.
.
0324
0360
.
.
.
0648
2
0684
.
.
.
0972
3
1008
.
.
.
1296
4
1332
.
.
.
.
1692
5
1728
.
.
.
.
2088
6
2124
.
.
.
2412
7
2448
.
.
.
2736
8
2772
.
.
.
3060
3096
.
.
.
3384
3420
3476, 3477 ... Electronic Signature
... 3538, 3539
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
M
L
S
S
B
B
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
8
OLMC
S0
19
3456
S1
3457
8
OLMC
S0
18
3458
S1
3459
8
OLMC
SO
17
3460
S1
3461
8
OLMC
S0
16
3462
S1
3463
10
OLMC
S0
15
3464
S1
3465
10
OLMC
S0
14
3466
S1
3467
8
OLMC
S0
13
3468
S1
3469
8
OLMC
S0
12
3470
S1
3471
8
OLMC
S0
11
3472
S1
3473
8
OLMC
S0
9
3474
S1
3475
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
5
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