FM24CL64-S Просмотр технического описания (PDF) - Unspecified

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производитель

FM24CL64-S

64Kb Serial 3V FRAM Memory

Unspecified 

FM24CL64

Counter

Address

Latch

2,048 x 32

FRAM Array

8

SDA

`

SCL

WP

A0-A2

Serial to Parallel

Converter

Control Logic

Data Latch

Figure 1. FM24CL64 Block Diagram

Pin Description

Pin Name

A0-A2

Type

Input

SDA

I/O

SCL

WP

VDD

VSS

Input

Input

Supply

Supply

Pin Description

Address 0-2. These pins are used to select one of up to 8 devices of the same type on

the same two-wire bus. To select the device, the address value on the three pins must

match the corresponding bits contained in the device address. The address pins are

pulled down internally.

Serial Data Address. This is a bi-directional line for the two-wire interface. It is

open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.

The input buffer incorporates a Schmitt trigger for noise immunity and the output

driver includes slope control for falling edges. A pull-up resistor is required.

Serial Clock. The serial clock line for the two-wire interface. Data is clocked out of

the part on the falling edge, and in on the rising edge. The SCL input also

incorporates a Schmitt trigger input for noise immunity.

Write Protect. When tied to VDD, addresses in the entire memory map will be write-

protected. When WP is connected to ground, all addresses may be written. This pin

is pulled down internally.

Supply Voltage: 2.7V to 3.6V

Ground

Rev 2.0

July 2003

Page 2 of 14

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