FIN1025 Просмотр технического описания (PDF) - Fairchild Semiconductor
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FIN1025 Datasheet PDF : 7 Pages
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June 2002
Revised June 2002
FIN1025
3.3V LVDS 2-Bit High Speed Differential Driver
General Description
This dual driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates LVTTL signal levels to LVDS lev-
els with a typical differential output swing of 350mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed trans-
fer of clock and data.
The FIN1025 can be paired with its companion receiver,
the FIN1026, or any other LVDS receiver.
Features
s Greater than 400Mbs data rate
s Flow-through pinout simplifies PCB layout
s 3.3V power supply operation
s 0.4ns maximum differential pulse skew
s 1.7ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Meets or exceeds the TIA/EIA-644 LVDS standard
s 14-Lead TSSOP package saves space
Ordering Code:
Order Number Package Number
Package Description
FIN1025MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
DIN1, DIN2,
DOUT1+, DOUT2+
DOUT1−, DOUT2−
EN
EN
VCC
GND
NC
Description
LVTTL Data Inputs
Non-Inverting Driver Outputs
Inverting Driver Outputs
Driver Enable Pin
Inverting Driver Enable Pin
Power Supply
Ground
No Connect
Truth Table
Inputs
EN
EN
H
L or OPEN
H
L or OPEN
H
L or OPEN
X
H
L or OPEN
X
H = HIGH Logic Level
L = LOW Logic Level
X = Don’t Care
Z = High Impedance
DIN
H
L
OPEN
X
X
Outputs
DOUT+
H
L
L
Z
Z
DOUT−
L
H
H
Z
Z
© 2002 Fairchild Semiconductor Corporation DS500783
www.fairchildsemi.com
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