AS4LC4M4883C Просмотр технического описания (PDF) - Austin Semiconductor
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AS4LC4M4883C Datasheet PDF : 20 Pages
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AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
EARLY WRITE CYCLE
tRC
tRAS
tRP
RAS
V
V
IH
IL
tCSH
tRSH
tCRP
tRCD
tCAS
CAS
V
V
IH
IL
,,, ,,,, ,,,,, ADDR
V
V
IH
IL
,,,,,,,,,,, ,,,,,,, , WE VIH
V IL
,,,,,,,,,, ,,,,,,,,,, DQVVIIOOHL
, , , , ,,,,,,,,,, OE
V
V
IH
IL
tASR
tRAD
tRAH
ROW
tWRP tWRH
NOTE 1
tAR
tASC
tRAL
tCAH
tWCS
COLUMN
tCWL
tRWL
tWCR
tWCH
tWP
tACH
tDHR
tDS
tDH
VALID DATA
ROW
DON’T CARE
UNDEFINED
NOTE:
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
tCRP
tCSH
tCWL
tDH
tDHR
tDS
tRAD
tRAH
-6
MIN MAX
15
45
0
0
10
12 10,000
5
50
15
10
40
0
15 30
10
-7
MIN MAX
15
55
0
0
15
15 10,000
5
55
15
12
50
0
15
35
10
-8
MIN MAX UNITS
20
ns
60
ns
0
ns
0
ns
15
ns
20 10,000 ns
5
ns
60
ns
20
ns
15
ns
55
ns
0
ns
15 40 ns
10
ns
SYM
tRAL
tRAS
tRC
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
-6
MIN MAX
30
60 10,000
110
16
45
40
13
15
10
40
0
10
10
10
-7
MIN MAX
35
70 10,000
130
16 50
50
15
15
12
50
0
12
10
10
-8
MIN MAX
40
80 10,000
150
20 60
60
0
20
15
60
0
15
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS4LC4M4
Rev. 11/97
DS000022
2-82
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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