MT4LC4M16R6TG-5(2001) Просмотр технического описания (PDF) - Micron Technology

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MT4LC4M16R6TG-5
(Rev.:2001)

4 MEG x 16 EDO DRAM

Micron Technology 

RAS# VVIIHL

CAS# VVIIHL

4 MEG x 16

EDO DRAM

ADDR

V

V

IH

IL

ROW

COLUMN (A)

COLUMN (B)

COLUMN (C)

COLUMN (D)

DQ

V IOH

V IOL

OE#

V IH

V IL

OPEN

VALID DATA (A)

tOD

tOES

tOE

VALID DATA (A)

VALID DATA (B)

tOD

tOEHC

VALID DATA (C)

tOD

tOEP

VALID DATA (D)

The DQs go back to

Low-Z if tOES is met.

The DQs remain High-Z

until the next CAS# cycle

if tOEHC is met.

Figure 3

OE# Control of DQs

The DQs remain High-Z

until the next CAS# cycle

if tOEP is met.

RAS# VVIIHL

CAS#

V

V

IH

IL

ADDR

V IH

V IL

DQ

V IOH

V IOL

WE#

V

V

IH

IL

OE#

V

V

IH

IL

ROW

COLUMN (A)

OPEN

VALID DATA (A)

tWHZ

tWPZ

COLUMN (B)

COLUMN (C)

VALID DATA (B)

tWHZ

INPUT DATA (C)

COLUMN (D)

The DQs go to High-Z if WE# falls and, if tWPZ is met,

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

Figure 4

WE# Control of DQs

WE# may be used to disable the DQs to prepare

for input data in an EARLY WRITE cycle. The DQs

will remain High-Z until CAS# goes LOW with

WE# HIGH (i.e., until a READ cycle is initiated).

DON’T CARE

UNDEFINED

4 Meg x 16 EDO DRAM

D29_C.p65 – Rev. 2/01

5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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