FAN5026 Просмотр технического описания (PDF) - Fairchild Semiconductor
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FAN5026 Datasheet PDF : 17 Pages
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Pin Definitions (Continued)
Pin
Number
13
14
15
16
18
28
Pin Name
DDR
VIN
PG1
PG2 /
REF2OUT
ILIM2 /
REF2
VCC
Pin Function Description
DDR Mode Control. High = DDR mode. Low = 2 separate regulators operating 180° out
of phase.
Input Voltage. Normally connected to battery, provides voltage feed-forward to set the
amplitude of the internal oscillator ramp. When using the IC for 2-step conversion from 5V
input, connect through 100K to ground, which will set the appropriate ramp gain and
synchronize the channels 90° out of phase.
Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a
±10% range of the 0.9V reference.
Power Good 2. When not in DDR Mode: Open-drain output that pulls LOW when the
VOUT is out of regulation or in a fault condition
Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically
used as the VDDQ/2 reference.
Current Limit 2. When not in DDR Mode, A resistor from this pin to GND sets the current
limit.
Reference for reg #2 when in DDR Mode. Typically set to VOUT1/2.
VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate
when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops
below 4.3V (UVLO falling).
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired.
Functional operation under these conditions is not implied.
Parameter
Min.
Typ.
Max.
Units
VCC Supply Voltage
6.5
V
VIN
18
V
BOOT, SW, ISNS, HDRV
24
V
BOOT to SW
6.5
V
All Other Pins
–0.3
VCC+0.3
V
Junction Temperature (TJ)
Storage Temperature
–40
150
°C
–65
150
°C
Lead Soldering Temperature, 10 seconds
300
°C
Recommended Operating Conditions
Parameter
Supply Voltage VCC
Supply Voltage VIN
Ambient Temperature (TA)
Conditions
note 1
Min.
4.75
–40
Typ.
5
Max.
5.25
16
85
Units
V
V
°C
4
FAN5026 Rev. 1.0.5
www.fairchildsemi.com
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