EVB71120-315-C(2015) Просмотр технического описания (PDF) - Melexis Microelectronic Systems

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EVB71120-315-C
(Rev.:2015)

300 to 930MHz Receiver Evaluation Board Description

Melexis Microelectronic Systems  

EVB71120

300 to 930MHz Receiver

Evaluation Board Description

1 Theory of Operation

1.1 General

The MLX71120 receiver architecture is based on a double-conversion super-heterodyne approach. The two

LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency is

derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high degree

of image rejection is provided even without using an RF front-end filter. At applications asking for very high

image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA.

The second mixer MIX2 is an image-reject mixer.

The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion

mixers (MIX1, MIX2) and an external IF filter with an on-chip amplifier (IFA). By choosing the required

modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or

the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the

demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by

means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data

signal can be performed by a noise filter (NF) building block.

The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to

setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the

RF signal differentially.

A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize

power dissipation.

A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a

microcontroller. The clock output is open drain and gets activated through a load connected to positive

supply.

1.2 Technical Data Overview

 Input frequency ranges: 300 to 470MHz

610 to 930MHz

 Power supply range: 2.1 to 5.5V

 Temperature range: -40 to +125°C

 Shutdown current: 50 nA

 Operating current: 6.5 to 8.1mA

 Selectable IF2 frequency: 10.7MHz or 455kHz

 FSK deviation range: ±10kHz to ±100kHz (WB)

±2kHz to ±10kHz (NB)

 Image rejection:

65dB 1st IF (with external RF front-end filter)

25dB 2nd IF (internal image rejection)

 Maximum data rate: 50kps RZ (bi-phase) code,

100kps NRZ

 Spurious emission: < -54dBm

 Linear RSSI range: > 70dB

 Crystal reference frequency: 16 to 27MHz

 MCU clock frequency: 2.0 to 3.4

 Input Sensitivity: at 4kbps NRZ, BER = 3·10-3

Frequency

315 MHz 433.92 MHz 868.3 MHz

FSK

wide band 180kHz BW, IF2=10.7MHz

f = ±20kHz

narrow band 20kHz BW, IF2=455kHz

f = ±5kHz

-109dBm

-114dBm

-108dBm

-112dBm

-106dBm

-111dBm

ASK wide band 180kHz BW, IF2=10.7MHz -113dBm -113dBm -111dBm

Note: - Sensitivities given for RF input 1 (without SAW filter)

- Sensitivity for RF input 2 is about 2 to 3dB worse (because of SAW filter loss)

915 MHz

-104dBm

-109dBm

-109dBm

39012 71120 01

Rev. 006

Page 3 of 18

EVB Description

Nov/15

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