MAX7000B Просмотр технического описания (PDF) - Altera Corporation

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MAX7000B

Programmable Logic Device

Altera Corporation 

MAX 7000B Programmable Logic Device Data Sheet

The Altera development system automatically optimizes product-term

allocation according to the logic requirements of the design.

For registered functions, each macrocell flipflop can be individually

programmed to implement D, T, JK, or SR operation with programmable

clock control. The flipflop can be bypassed for combinatorial operation.

During design entry, the designer specifies the desired flipflop type; the

MAX+PLUS II software then selects the most efficient flipflop operation

for each registered function to optimize resource utilization.

Each programmable register can be clocked in three different modes:

■ Global clock signal. This mode achieves the fastest clock-to-output

performance.

■ Global clock signal enabled by an active-high clock enable. A clock

enable is generated by a product term. This mode provides an enable

on each flipflop while still achieving the fast clock-to-output

performance of the global clock.

■ Array clock implemented with a product term. In this mode, the

flipflop can be clocked by signals from buried macrocells or I/O pins.

Two global clock signals are available in MAX 7000B devices. As shown

in Figure 1, these global clock signals can be the true or the complement of

either of the global clock pins, GCLK1 or GCLK2.

Each register also supports asynchronous preset and clear functions. As

shown in Figure 2, the product-term select matrix allocates product terms

to control these operations. Although the product-term-driven preset and

clear from the register are active high, active-low control can be obtained

by inverting the signal within the logic array. In addition, each register

clear function can be individually driven by the active-low dedicated

global clear pin (GCLRn). Upon power-up, each register in a MAX 7000B

device may be set to either a high or low state. This power-up state is

specified at design entry.

All MAX 7000B I/O pins have a fast input path to a macrocell register.

This dedicated path allows a signal to bypass the PIA and combinatorial

logic and be clocked to an input D flipflop with an extremely fast input

setup time. The input path from the I/O pin to the register has a

programmable delay element that can be selected to either guarantee zero

hold time or to get the fastest possible set-up time (as fast as 1.0 ns).

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Altera Corporation

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