EP7212-CV-A Просмотр технического описания (PDF) - Cirrus Logic
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EP7212-CV-A Datasheet PDF : 136 Pages
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EP7212
5.16.3.4 Left Channel Receive FIFO Service Request Flag (LCRS) ....................... 94
5.16.3.5 Right Channel Transmit FIFO Underrun Status (RCTU) ........................... 94
5.16.3.6 Right Channel Receive FIFO Overrun Status (RCRO) ............................. 94
5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU) .............................. 95
5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO) ................................ 95
5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF) ................................. 95
5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE) ........................... 95
5.16.3.11 Left Channel Transmit FIFO Not Full Flag (LCNF) .................................. 95
5.16.3.12 Left Channel Receive FIFO Not Empty Flag (LCNE) .............................. 95
5.16.3.13 FIFO Operation Completed Flag (FIFO) .................................................. 95
6. ELECTRICAL SPECIFICATIONS .......................................................................................... 96
6.1 Absolute Maximum Ratings .............................................................................................. 96
6.2 Recommended Operating Conditions .............................................................................. 96
6.3 DC Characteristics ............................................................................................................ 96
6.4 AC Characteristics ............................................................................................................ 98
6.5 I/O Buffer Characteristics ................................................................................................ 110
6.6 JTAG Boundary Scan Signal Ordering ........................................................................... 111
7. TEST MODES ....................................................................................................................... 114
7.1 Oscillator and PLL Bypass Mode .................................................................................... 114
7.2 Oscillator and PLL Test Mode ......................................................................................... 114
7.3 Debug / ICE Test Mode .................................................................................................. 115
7.4 Hi-Z (System) Test Mode ............................................................................................... 115
7.5 Software Selectable Test Functionality .......................................................................... 115
8. PIN INFORMATION .............................................................................................................. 116
8.1 208-Pin LQFP Pin Diagram ............................................................................................. 116
8.2 208-Pin LQFP Numeric Pin Listing ................................................................................. 117
8.3 256-Pin PBGA Pin Diagram ............................................................................................ 120
8.4 256-Ball PBGA Ball Listing .............................................................................................. 121
9. PACKAGE SPECIFICATIONS ............................................................................................. 125
9.1 208-Pin LQFP Package Outline Drawing ....................................................................... 125
9.2 EP7212 256-Ball PBGA (17 × 17 × 1.53-mm Body) Dimensions ................................... 126
10. ORDERING INFORMATION ............................................................................................... 127
11. APPENDIX A: BOOT CODE .............................................................................................. 128
12. INDEX ................................................................................................................................. 133
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