EM78862C Просмотр технического описания (PDF) - ELAN Microelectronics

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EM78862C

8-Bit Microcontroller

ELAN Microelectronics 

EM78862C

8-Bit RISC Type Microprocessor

OSCI

OSCO

32.768kHz

RC/Crystal

OSC

Fosc

0

PLL FPLL 1

Fsystem

"OSC_SEL "bit PLL_EN

of code option

Fig. 5 The Relation between 32.768KHz and 3.579MHz

Bit 7 (IDLE): Power saving mode control register

When PLL is disabled, you can set this bit with SLEP instruction to define

SLEEP/IDLE mode selection, i.e., 0/1 → SLEEP mode/IDLE mode.

This bit determines which mode will be set for SLEP instruction.

Wakeup Signal SLEEP Mode

RA(7,6)=(0,0)

+ SLEP

TCC

Time-Out

X

Counter 1

Time-Out

X

Counter 2

Time-Out

X

Port7.0 ~ 7.7

(INT0~2)

WDT

Time-Out

RESET

RESET

IDLE Mode

RA(7,6)=(1,0)

+ SLEP

Wake-up

+ Interrupt

+ Next instruction

Wake-up

+ Interrupt

+ Next instruction

Wake-up

+ Interrupt

+ Next instruction

Wake-up

+ Interrupt

+ Next instruction

Wake-up

+ Next instruction

GREEN Mode

RA(7,6)=(x,0)

no SLEP

Interrupt

(jump to address

8 at page0)

Interrupt

(jump to address

8 at page0)

Interrupt

(jump to address

8 at page0)

Interrupt

(jump to address

8 at page0)

RESET

NORMAL Mode

RA(7,6)=(x,1)

no SLEP

Interrupt

(jump to address

8 at page0)

Interrupt

(jump to address

8 at page0)

Interrupt

(jump to address

8 at page0)

Interrupt

(jump to address

8 at page0)

RESET

NOTE

1. PORT 70 ~ PORT 73's wake-up function is controlled by IOCF Bit 3 and ENI

instruction. They are triggered by a falling edge.

2. PORT 74 ~ PORT 76's wake-up function is controlled by IOCF Bit 4 and ENI

instruction. They are triggered by a falling edge.

3. PORT 77's wake-up function is controlled by IOCF Bit 5 and ENI instruction. It is

triggered by a falling edge or a rising edge (controlled by CONT register).

Product Specification (V2.1) 07.13.2005

(This specification is subject to change without further notice)

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