EM6A9320BI-3.6 Просмотр технического описания (PDF) - Etron Technology

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EM6A9320BI-3.6

4M x 32 DDR SDRAM

Etron Technology 

EtronTech 4Mx32 DDR SDRAM

EM6A9320

VSS

Supply Ground: Ground for the input buffers and core logic.

VDDQ

Supply DQ Power: Provide isolated power to DQs for improved noise immunity.

VSSQ

Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

VREF

Supply Reference Voltage for Inputs: +0.5 x VDDQ

NC

- No Connect: These pins should be left unconnected.

Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any

applications using the single ended clocking, apply VREF to CK# pin.

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CK . Table 2

shows the truth table for the operation commands.

Table 2. Truth Table (Note (1), (2) )

Command

State CKEn-1 CKEn DM BA1 BA0 A8 A11-A9, A7-0 CS# RAS# CAS# WE#

BankActivate

Idle(3)

H

X X V V Row Address L L H H

BankPrecharge

Any

H

X XVVL

X

LL HL

PrechargeAll

Any

H

X XXXH

X

LL HL

Write

Active(3)

H

X VVVL

LH LL

Write and AutoPrecharge

Active(3)

H

X

V

V

V

H

Column

Address

L

H

LL

Read

Active(3)

H

X X V V L A0~A7 L H

LH

Read and Autoprecharge Active(3)

H

X XVVH

LH LH

Mode Register Set

Idle

Extended Mode Register Set

Idle

H

X XLL

OP code

LL LL

H

X XLH

LL LL

No-Operation

Any

H

X XXXX

X

LH HH

Device Deselect

Any

H

X XXXX

X

HX XX

Burst Stop

Active(4)

H

X XXXX

X

LH HL

AutoRefresh

Idle

H H XXXX

X

LL LH

SelfRefresh Entry

Idle

H

L XXXX

X

LL LH

SelfRefresh Exit

Idle

HX XX

L

H XXXX

X

(Self Refresh)

LH HH

Power Down Mode Entry Idle/Active(5) H

L XXXX

X

HX XX

LH HH

Power Down Mode Exit

Any

L

H XXXX

X

HX XX

(Power Down)

LH HH

Data Write/Output Enable

Active

H

X LXXX

X

XX XX

Data Mask/Output Disable Active

H

X HXXX

X

XX XX

Note:

1. V = Valid data, X = Don't Care, L = Low level, H = High level

2. CKEn signal is input level when commands are provided.

CKEn-1 signal is input level one clock cycle before the commands are provided.

3. These are states of bank designated by BA0, BA1signals.

4. Read burst stop with BST command for all burst types.

5. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.

5

Rev 0.6

May. 2006

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