EL7558D Просмотр технического описания (PDF) - Intersil
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EL7558D Datasheet PDF : 11 Pages
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EL7558D
selects FB1 and allows the output to be programmed from
1.0 to 3.8V. In general:
VOUT
=
1.0 V
×
1
+
R-----3-
R4
× Volt
However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and loop-
gain are changed. This is shown in the performance curves.
(The output voltage is factory trimmed to minimize error at a
2.50V output). A 2µA pull-up current from FB1 to VIN forces
VOUT to GND in the event that FB1 is not used and the
VCC2DET is inadvertently toggled between the internal and
external feedback mode of operation.
NMOS Power FETS and Drive Circuitry
The EL7558D integrates low resistance (25mΩ) NMOS
FETS to achieve high efficiency at 8A. Gate drive for both
the high-side and low-side switches is derived through a
charge pump consisting of the CP pin and external
components D1-D3 and C5-C6. The CP output is a low
resistance inverter driven at one-half the oscillator frequency.
This is used in conjunction with D2-D3 to generate a 7.5V
(typical) voltage on the C2V pin which provides gate drive to
the low-side NMOS switch and associated level shifter. In
order to use an NMOS switch for the high-side drive it is
necessary to drive the gate voltage above the source voltage
(LX). This is accomplished by boot-strapping the VHI pin
above the C2V voltage with capacitor C6 and diode D1.
When the low-side switch is turned on the LX voltage is
close to GND potential and capacitor C6 is charged through
diodes D1-D3 to approximately 6.9V. At the beginning of the
next cycle the high side switch turns on and the LX pin
begins to rise from GND to VDD potential. As the LX pin
rises the positive plate of capacitor C6 follows and eventually
reaches a value of approximately 11.2V, for VDD=5V. This
voltage is then level shifted and used to drive the gate of the
high-side FET, via the VHI pin.
Reference
A 1% temperature compensated band gap reference is
integrated in the EL7558D. The external CREF capacitor
acts as the dominant pole of the amplifier and can be
increased in size to maximize transient noise rejection. A
value of 0.1uF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 96%.
Operating frequency can be adjusted through the COSC pin
or can be driven by an external clock source. If the oscillator
is driven by an external source, care must be taken in the
selection of CSLOPE. Since the COSC and CSLOPE values
determine the open loop gain of the system, changes to
COSC require corresponding changes to CSLOPE in order
to maintain a constant gain ratio. The recommended ratio of
COSC to CSLOPE is 1.5:1
Temperature Sensor
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the OT pin will output a logic 0. The upper
and lower trip points are set to 135°C and 100°C
respectively. To enable thermal shutdown this pin should be
tied directly to OUTEN. Use of this feature is recommended
during normal operation.
Power Good and Power On Reset
During power up the output regulator will be disabled until
VIN reaches 4.0V. Approximately 500mV of hysteresis is
present to eliminate noise induced oscillations.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
A logic 1 on the PWRGD output indicates that regulated
output voltage is within ±10% of the nominally programmed
output voltage. Although small, the typical values of the
PWRGD threshold will vary with changes to external
feedback (and resultant loop gain) of the system. This
dependence is shown in the typical performance curves.
Thermal Management
The EL7558D utilizes HSOP packaging technology in
conjunction with the system board layout to achieve a lower
thermal resistance than typically found in standard 28 lead
SOIC packages. By attaching the die directly to an exposed
metal slug embedded within the package body, thermal
energy flows through a thermally conductive path (metal)
instead of thermally resistive plastic. After conducting heat
from the die to the PCB, heat transfer occurs by convection.
If a significant amount of metal on the PCB is connected to
the exposed heat slug, a junction-to-ambient resistance of
31°C/W can be achieved compared to 100°C/W found in
standard packages. It can be readily seen that the thermal
resistance approaches an asymptotic value of approximately
31°C/W. Additional information can be found in Application
Note #8 (Measuring the Thermal Resistance of Power
Surface-Mount Packages), and Application Note #13
(EL75XX Thermal Design Considerations).
If the thermal shutdown pin is connected to OUTEN the IC
will enter thermal shutdown when the maximum junction
temperature is reached. For a thermal shutdown of 135°C
and power dissipation of 2.2W the ambient temperature is
limited to a maximum value of 67°C (typical). The ambient
temperature range can be extended with the application of
air flow. For example, the addition of 100LFM reduces the
thermal resistance by approximately 15% and can extend
the operating ambient to 77°C (typical). Since the thermal
performance of the IC is heavily dependent on the board
layout, the system designer should exercise care during the
design phase to ensure that the IC will operate under the
worst-case environmental conditions.
10
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