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EL5224IRE-T7 Просмотр технического описания (PDF) - Intersil

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производитель
EL5224IRE-T7 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
EL5224, EL5324, EL5424
Typical Performance Curves (Continued)
M=4µs/DIV, VS=±7.5V, VIN=0V
0mA
-100mA
100mA/DIV
M=4µs/DIV, VS=±7.5V, VIN=0V
100mA
0mA
0V
CL=1µF
20mV/DIV
0V
CL=1µF
100mA/DIV
20mV/DIV
FIGURE 13. TRANSIENT LOAD REGULATION - SOURCING
(VCOM)
VS=±7.5V, RL=10kΩ, CL=12pF
FIGURE 14. TRANSIENT LOAD REGULATION - SINKING
(VCOM)
VS=±7.5V
50mV/DIV
1V/DIV
200ns/DIV
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE
(BUFFER)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3
2.857W
2.5 2.703W
QFN32
2
θJA=35°C/W
1.5
QFN24
θJA=37°C/W
1
0.5
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
7
1µs/DIV
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE
(BUFFER)
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE
LAYER) TEST BOARD
0.8
758mW
0.7
714mW
0.6
QFN32
0.5
θJA=132°C/W
0.4
QFN24
θJA=140°C/W
0.3
0.2
0.1
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE

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