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EL4584C Просмотр технического описания (PDF) - Elantec -> Intersil

Номер в каталоге
Компоненты Описание
производитель
EL4584C
ELANTE-ElectronicC
Elantec -> Intersil ELANTE-ElectronicC
EL4584C Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
EL4584C
Horizontal Genlock 4 FSC
AC Electrical Characteristics (VDD e 5V TA e 25 C unless otherwise noted)
Parameter
Conditions
Temp
Min
Typ
Max
VCO Gain 20 MHz
Test Circuit 1
25 C
15 5
H-sync S N Ratio
VDD e 5V (Note 2)
25 C
35
Jitter
VCXO Oscillator
25 C
1
Jitter
LC Oscillator (Typ)
25 C
10
Note 2 Noisy video signal input to EL4583C H-sync input to EL4584C Test for positive signal lock
Test
Level
V
V
V
V
Units
dB
dB
ns
ns
Pin Description
Pin No Pin Name
Function
16 1 2 Prog A B C
Digital inputs to select d N value for internal counter See table below for values
3
Osc VCO Out Output of internal inverter oscillator Connect to external crystal or LC tank VCO circuit
4
VDD (A)
Analog positive supply for oscillator PLL circuits
5
Osc VCO In
Input from external VCO
6
VSS (A)
Analog ground for oscillator PLL circuits
7
Charge Pump Out Connect to loop filter If the H-sync phase is leading or H-sync frequency l CLKdN current is pumped
into the filter capacitor to increase VCO frequency If H-sync phase is lagging or frequency k CLKdN
current is pumped out of the filter capacitor to decrease VCO frequency During coast mode or when
locked charge pump goes to a high impedance state
8
Div Select
Divide select input When high the internal divider is enabled and EXT DIV becomes a test pin
outputting CLKdN When low the internal divider is disabled and EXT DIV is an input from an
external dN
9
Coast
10
H-sync In
Tri-state logic input Low(k VCC) e normal mode Hi Z(or to
High(l VCC) e coast mode
Horizontal sync pulse (CMOS level) input
VCC) e fast lock mode
11
VDD (D)
12
Lock Det
Positive supply for digital I O circuits
Lock Detect output Low level when PLL is locked Pulses high when out of lock
13
Ext Div
External Divide input when DIV SEL is low internal dN output when DIV SEL is high
14
VSS (D)
15
CLK Out
Ground for digital I O circuits
Buffered output of the VCO
Prog A
Pin 16
0
0
0
0
1
1
1
1
VCO Divisors Table 1
Prog B
Pin 1
Prog C
Pin 2
Div Value
N
0
0
851
0
1
864
1
0
944
1
1
1135
0
0
682
0
1
858
1
0
780
1
1
910
3

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