EL2120CN Просмотр технического описания (PDF) - Intersil
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EL2120CN Datasheet PDF : 12 Pages
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EL2120
be used to reduce resonances. This is a resistor and
capacitor in series connected from output to ground. Values
of 68Ω and 33pF are typical. Increasing the feedback
resistor can also improve frequency flatness.
The VIN+ pin can oscillate in the 200MHz to 500MHz realm if
presented with a resonant or inductive source impedance. A
series 27Ω to 68Ω resistor right on the VIN+ pin will suppress
such oscillations without affecting frequency response.
-3dB bandwidth is inversely proportional to the value of
feedback resistor RF. The EL2120 will tolerate values as low
as 180Ω for a maximum bandwidth of about 140MHz, but
peaking will increase and tolerance to stray capacitance will
reduce. At gains greater than 5, -3dB bandwidth begins to
reduce, and a smaller RF can be used to maximize
frequency response.
The greatest frequency response flatness (to 0.1dB, for
instance) occurs with RF = 300Ω to 330Ω. Even the
moderate peaking caused by lower values of RF will cause
the gain to peak out of the 0.1dB window, and higher values
of RF will cause an overcompensated response where the
gain falls below the 0.1dB level. Parasitic capacitances will
generally degrade the frequency flatness.
The EL2120 should not output a continuous current above
50mA, as stated in the ABSOLUTE MAXIMUM RATINGS
table. The output current limit is set to 120mA at a die
temperature of 25°C and reduces to 85mA at a die
temperature of 150°C. This large current is needed to slew
load capacitance and drive low impedance loads with low
distortion but cannot be supported continuously.
Furthermore, package dissipation capabilities cannot be met
under short-circuit conditions. Current limit should not occur
longer than a few seconds.
The output disable function of the EL2120 is optimized for
video performance. While in disable mode, the feedthrough
of the circuit can be modeled as a 0.2pF capacitor from VIN+
to the output. No more than ±5V can be placed between
VIN+ and VIN- in disable mode, but this is compatible with
common video signal levels. In disabled state the output can
withstand about 1000V/µs slew rate signals impressed on it
without the output transistors turning on.
The /Disable pin logic level is referred to V+. With ±5V
supplies, a CMOS or TTL driver with pull-up resistor will
suffice. ±15V supplies require a +14/+11V drive span, or
+15/+10V nominally. Open-collector TTL with a tapped pull-
up resistor can provide these spans. The impedance of the
divider should be 1k or less for optimum enable/disable
speed.
The EL2120 enables in 50ns or less. When VIN = 0, only a
small switching glitch occurs at the output. When VIN is
some other value, the output overshoots by about 0.7V when
settling toward its new enabled value.
When the EL2120 disables, it turns off very rapidly for inputs
of ±1V or less, and the output sags more slowly for inputs
larger than this. For inputs as large as ±2.5V the output
current can be absorbed by another EL2120 simultaneously
enabled. Under these conditions, switching will be properly
completed in 50ns or less.
The greater thermal resistance of the SO-8 package
requires that the EL2120 be operated from ±10V supplies or
less to maintain the 150°C maximum die temperature over
the commercial temperature range. The P-DIP package
allows the full ±16.5V supply operation.
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