DS7505(2015) Просмотр технического описания (PDF) - Maxim Integrated
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DS7505 Datasheet PDF : 14 Pages
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DS7505
Digital Thermometer and Thermostat
General 2-Wire Information
●● All data is transmitted MSB first over the 2-wire bus.
●● One bit of data is transmitted on the 2-wire bus each
SCL period.
●● A pullup resistor is required on the SDA line, and,
when the bus is idle, both SDA and SCL must remain
in a logic-high state.
●● All bus communication must be initiated with a START
condition and terminated with a STOP condition. Dur-
ing a START or STOP is the only time SDA is allowed
to change states while SCL is high. At all other times,
changes on the SDA line can only occur when SCL is
low; SDA must remain stable when SCL is high.
●● After every 8-bit (1-byte) transfer, the receiving device
must answer with an ACK (or NACK), which takes
one SCL period. Therefore, nine clocks are required
for every 1-byte data transfer.
Writing to the DS7505: To write to the DS7505, the
master must generate a START followed by an address
byte containing the DS7505 bus address. The value of
the R/W bit must be a 0, which indicates that a write is
about to take place. The DS7505 responds with an ACK
after receiving the address byte. The master then sends
a pointer byte which tells the DS7505 which register is
being written to. The DS7505 again responds with an
ACK after receiving the pointer byte. Following this ACK
the master device must immediately begin transmitting
data to the DS7505. When writing to the configuration
register, the master must send one byte of data (see
Figure 9B), and when writing to the TOS or THYST
registers the master must send two bytes of data (see
Figure 9C). After receiving each data byte, the DS7505
responds with an ACK, and the transaction is finished
with a STOP from the master. All writes to the DS7505
are made to shadow SRAM. Once data is written to the
shadow SRAM, it is only stored to EEPROM by issuance
of a Copy Data command from the master. At that time, all
registers are copied to EEPROM except the Temperature
register which is SRAM only.
Reading from the DS7505: When reading from the
DS7505, if the pointer was already pointed to the desired
register during a previous transaction, the read can be
performed immediately without changing the pointer set-
ting. In this case the master sends a START followed by
an address byte containing the DS7505 bus address.
The R/W bit must be a 1, which tells the DS7505 that
a read is being performed. After the DS7505 sends an
ACK in response to the address byte, the DS7505 begins
transmitting the requested data on the next clock cycle.
When reading from the configuration register, the DS7505
transmits one byte of data, after which the master must
respond with a NACK followed by a STOP (see Figure
9E). For two-byte reads (i.e., from the temperature, TOS
or THYST register), the DS7505 transmits two bytes of
data, and the master must respond to the first data byte
with an ACK and to the second byte with a NACK followed
by a STOP (see Figure 9A). If only the most significant
byte of data is needed, the master can issue a NACK fol-
lowed by a STOP after reading the first data byte in which
case the transaction is the same as for a read from the
configuration register.
If the pointer is not already pointing to the desired register,
the pointer must first be updated as shown in Figure 9D,
which shows a pointer update followed by a single-byte
read. The value of the R/W bit in the initial address byte
is a 0 (“write”) since the master is going to write a pointer
byte to the DS7505. After the DS7505 responds to the
address byte with an ACK, the master sends a pointer
byte that corresponds to the desired register. The master
must then perform a repeated start followed by a stan-
dard one or two byte read sequence (with R/W =1) as
described in the previous paragraph.
The Recall Data command should be issued before a
read if assurance is needed that the contents of the
EEPROM in the Shadow SRAM when read.
Bus Timeout: The DS7505 has a bus timeout feature
that prevents communication errors from leaving the IC in
a state where SDA is held low disrupting other devices on
the bus. If the DS7505 holds the SDA line low for a period
of tTIMEOUT, its bus interface automatically resets and
release the SDA line. Bus communication frequency must
be fast enough to prevent a reset during normal opera-
tion. The bus timeout feature only applies to when the
DS7505 is holding SDA low. Other devices can hold SDA
low for an undefined period without causing the interface
to reset.
Command Set
Recall Data [B8h]
1011 1000
Refreshes SRAM shadow register with EEPROM data.
It is recommended that a Recall command be performed
before reading EEPROM-backed memory locations. The
master sends a START followed by an address byte con-
taining the DS7505 bus address. The R/W bit must be a
0. The DS7505 responds with an ACK. If the next byte is a
0xB8, the DS7505 recalls all EEPROM data into shadow
RAM locations.
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