DS28E15 Просмотр технического описания (PDF) - Maxim Integrated

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DS28E15

1-Wire SHA-256 Secure Authenticator with 512-Bit User EEPROM

Maxim Integrated 

ABRIDGED DATA SHEET

DS28E15

1-Wire SHA-256 Secure Authenticator

with 512-Bit User EEPROM

ELECTRICAL CHARACTERISTICS (continued)

(TA = -40NC to +85NC, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

EEPROM

Programming Current

Programming Time for a 32-Bit

Segment

IPROG

tPROG

VPUP = 3.63V (Notes 5, 18)

(Note 19)

1

mA

10

ms

Write/Erase Cycling Endurance

Data Retention

SHA-256 ENGINE

NCY TA = +125NC (Notes 20, 21)

100k

tDR

TA = +125NC (storage) (Notes 22, 23, 24)

10

—

Years

Computation Current

ICSHA Refer to the full data sheet.

mA

Computation Time

tCSHA

ms

Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and

relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.

Note 2: System requirement.

Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery

times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.

Note 4: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is

charged, it does not affect normal communication.

Note 5: Guaranteed by design and/or characterization only. Not production tested.

Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and

capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values

of VTL, VTH, and VHY.

Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.

Note 8: The voltage on IO must be less than or equal to VIL(MAX) at all times the master is driving IO to a logic 0 level.

Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.

Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.

Note 11: The I-V characteristic is linear for voltages less than 1V.

Note 12: Applies to a single device attached to a 1-Wire line.

Note 13: Defines maximum possible bit rate. Equal to 1/(tW0L(MIN) + tREC(MIN)).

Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.

Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E15 present. The power-up pres-

ence detect pulse could be outside this interval but will be complete within 2ms after power-up.

Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual

maximum duration for the master to pull the line low is tW1L(MAX) + tF - ε and tW0L(MAX) + tF - ε, respectively.

Note 17: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high

threshold of the bus master. The actual maximum duration for the master to pull the line low is tRL(MAX) + tF.

Note 18: Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during

the programming and computation interval should be such that the voltage at IO is greater than or equal to VPUP(MIN). A

low-impedance bypass of RPUP activated during programming and computation is the recommended way to meet this

requirement.

Note 19: Refer to the full data sheet.

Note 20: Write-cycle endurance is tested in compliance with JESD47G.

Note 21: Not 100% production tested; guaranteed by reliability monitor sampling.

Note 22: Data retention is tested in compliance with JESD47G.

Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the-

data sheet limit at operating temperature range is established by reliability testing.

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