DS2751E Просмотр технического описания (PDF) - Maxim Integrated

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DS2751E

Multichemistry Battery Fuel Gauge

Maxim Integrated 

DS2751

I/O SIGNALING

The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the

DS2751 are: the initialization sequence (reset pulse followed by presence pulse), Write 0, Write 1, and

Read Data. All of these types of signaling except the presence pulse are initiated by the bus master.

The initialization sequence required to begin any communication with the DS2751 is shown in Figure 15.

A presence pulse following a reset pulse indicates the DS2751 is ready to accept a net address command.

The bus master transmits (Tx) a reset pulse for tRSTL. The bus master then releases the line and goes into

receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the

rising edge on the DQ pin, the DS2751 waits for tPDH and then transmits the Presence Pulse for tPDL.

Figure 15. 1-WIRE INITIALIZATION SEQUENCE

DQ

tRSTL

tPDH

tPDL

tRSTH

LINE TYPE LEGEND:

BUS MASTER ACTIVE LOW

BOTH BUS MASTER AND

DS2751 ACTIVE LOW

DS2751 ACTIVE LOW

RESISTOR PULLUP

PACK+

PACK–

WRITE TIME SLOTS

A write time slot is initiated when the bus master pulls the 1-Wire bus from a logic high (inactive) level to

a logic low level. There are two types of write time slots: Write 1 and Write 0. All write time slots must

be tSLOT (60ms to 120ms) in duration with a 1ms minimum recovery time, tREC, between cycles. The

DS2751 samples the 1-Wire bus line between 15ms and 60ms after the line falls. If the line is high when

sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs (see Figure 16). For the bus

master to generate a Write 1 time slot, the bus line must be pulled low and then released, allowing the line

to be pulled high within 15ms after the start of the write time slot. For the host to generate a Write 0 time

slot, the bus line must be pulled low and held low for the duration of the write time slot.

READ TIME SLOTS

A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high level to a

logic low level. The bus master must keep the bus line low for at least 1ms and then release it to allow the

DS2751 to present valid data. The bus master can then sample the data tRDV (15ms) from the start of the

read time slot. By the end of the read time slot, the DS2751 releases the bus line and allows it to be pulled

high by the external pullup resistor. All read time slots must be tSLOT (60ms to 120ms) in duration with a

1ms minimum recovery time, tREC, between cycles. See Figure 16 for more information.

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