DS26334G Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS26334G

3.3V, 16-Channel, E1/T1/J1 Short and Long-Haul Line Interface Unit

Dallas Semiconductor -> Maxim Integrated 

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

LIST OF FIGURES

Figure 3-1. Block Diagram ........................................................................................................................................... 8

Figure 3-2. Receive Logic Detail.................................................................................................................................. 9

Figure 3-3. Transmit Logic Detail................................................................................................................................. 9

Figure 5-1. Serial Port Operation for Write Access ................................................................................................... 17

Figure 5-2. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 17

Figure 5-3. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 18

Figure 5-4. Interrupt Handling Flow Diagram ............................................................................................................ 19

Figure 5-5. Prescaler PLL and Clock Generator ....................................................................................................... 20

Figure 5-6. T1 Transmit Pulse Templates ................................................................................................................. 23

Figure 5-7. E1 Transmit Pulse Templates ................................................................................................................. 24

Figure 5-8. LIU Front-End.......................................................................................................................................... 25

Figure 5-9. Jitter Attenuation ..................................................................................................................................... 31

Figure 5-10. Analog Loopback................................................................................................................................... 32

Figure 5-11. Digital Loopback.................................................................................................................................... 33

Figure 5-12. Remote Loopback ................................................................................................................................. 33

Figure 5-13. PRBS Synchronization State Diagram.................................................................................................. 36

Figure 5-14. Repetitive Pattern Synchronization State Diagram............................................................................... 37

Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 92

Figure 7-2. TAP Controller State Diagram................................................................................................................. 95

Figure 9-1. Intel Nonmuxed Read Cycle ................................................................................................................. 101

Figure 9-2. Intel Mux Read Cycle ............................................................................................................................ 102

Figure 9-3. Intel Nonmux Write Cycle...................................................................................................................... 104

Figure 9-4. Intel Mux Write Cycle ............................................................................................................................ 105

Figure 9-5. Motorola Nonmux Read Cycle .............................................................................................................. 107

Figure 9-6. Motorola Mux Read Cycle ..................................................................................................................... 108

Figure 9-7. Motorola Nonmux Write Cycle .............................................................................................................. 110

Figure 9-8. Motorola Mux Write Cycle ..................................................................................................................... 111

Figure 9-9. Serial Bus Timing Write Operation........................................................................................................ 112

Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 112

Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 112

Figure 9-12. Transmitter Systems Timing ............................................................................................................... 113

Figure 9-13. Receiver Systems Timing ................................................................................................................... 114

Figure 9-14. JTAG Timing ....................................................................................................................................... 115

Figure 10-1. 256-Ball TE-CSBGA............................................................................................................................ 116

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