DS26334G(2005) Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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Компоненты Описание

производитель

DS26334G
(Rev.:2005)

3.3V, 16-Channel, E1/T1/J1 Short- and Long-Haul Line Interface Unit

Dallas Semiconductor -> Maxim Integrated 

DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit

TABLE OF CONTENTS

1 STANDARDS COMPLIANCE ........................................................................................................ 6

1.1 TELECOM SPECIFICATIONS COMPLIANCE ....................................................................................... 6

2 DETAILED DESCRIPTION ............................................................................................................ 7

3 BLOCK DIAGRAMS ...................................................................................................................... 8

4 PIN DESCRIPTION ...................................................................................................................... 10

5 FUNCTIONAL DESCRIPTION ..................................................................................................... 18

5.1 PORT OPERATION ...................................................................................................................... 18

5.1.1 Serial Port Operation.............................................................................................................................. 18

5.1.2 Parallel Port Operation ........................................................................................................................... 19

5.1.3 Interrupt Handling................................................................................................................................... 19

5.2 POWER-UP AND RESET .............................................................................................................. 20

5.3 MASTER CLOCK ......................................................................................................................... 20

5.4 TRANSMITTER ............................................................................................................................ 21

5.4.1 Transmit Line Templates........................................................................................................................ 23

5.4.2 LIU Transmit Front End .......................................................................................................................... 26

5.4.3 Dual Rail ................................................................................................................................................. 27

5.4.4 Single-Rail Mode .................................................................................................................................... 27

5.4.5 Zero Suppression—B8ZS or HDB3 ....................................................................................................... 27

5.4.6 Transmit Power-Down............................................................................................................................ 27

5.4.7 Transmit All Ones................................................................................................................................... 28

5.4.8 Drive Failure Monitor .............................................................................................................................. 28

5.5 RECEIVER.................................................................................................................................. 28

5.5.1 Receiver Monitor Mode .......................................................................................................................... 28

5.5.2 Peak Detector and Slicer ....................................................................................................................... 28

5.5.3 Receive Level Indicator .......................................................................................................................... 28

5.5.4 Clock and Data Recovery ...................................................................................................................... 29

5.5.5 Loss of Signal......................................................................................................................................... 29

5.5.6 AIS.......................................................................................................................................................... 30

5.5.7 Bipolar Violation and Excessive Zero Detector ...................................................................................... 31

5.6 JITTER ATTENUATOR .................................................................................................................. 31

5.7 G.772 MONITOR ........................................................................................................................ 32

5.8 LOOPBACKS............................................................................................................................... 32

5.8.1 Analog Loopback.................................................................................................................................... 32

5.8.2 Digital Loopback..................................................................................................................................... 33

5.8.3 Remote Loopback .................................................................................................................................. 34

5.9 BERT........................................................................................................................................ 34

5.9.1 General Description................................................................................................................................ 34

5.9.2 Configuration and Monitoring ................................................................................................................. 35

5.9.3 Receive Pattern Detection ..................................................................................................................... 36

5.9.4 Transmit Pattern Generation.................................................................................................................. 38

6 REGISTER MAPS AND DEFINITION .......................................................................................... 39

6.1 REGISTER DESCRIPTION............................................................................................................. 48

6.1.1 Primary Register Bank ........................................................................................................................... 48

6.1.2 Secondary Register Bank ...................................................................................................................... 61

6.1.3 Individual LIU Register Bank.................................................................................................................. 64

6.1.4 BERT Registers...................................................................................................................................... 81

7 JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT ................................. 88

7.1 TAP CONTROLLER STATE MACHINE............................................................................................ 89

7.2 INSTRUCTION REGISTER ............................................................................................................. 92

7.3 TEST REGISTERS ....................................................................................................................... 93

7.4 BOUNDARY SCAN REGISTER....................................................................................................... 93

7.5 BYPASS REGISTER ..................................................................................................................... 93

7.6 IDENTIFICATION REGISTER.......................................................................................................... 93

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