DS2465P Просмотр технического описания (PDF) - Maxim Integrated

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DS2465P

SHA-256 Coprocessor with 1-Wire Master Function

Maxim Integrated 

ABRIDGED DATA SHEET

DS2465

SHA-256 Coprocessor with 1-Wire Master Function

1-Wire Master Reset

Command Code

Parameter Byte

Usage

Other Notes

Command Restrictions

Error Conditions (Error Response)

MAC Notes

I2C Busy Duration

Command Duration

1-Wire Activity

Read Pointer Position

Master Status Bits Affected

Master Configurations Affected

1-Wire Port Configurations Affected

F0h

N/A

Device initialization after power-up; re-initialization (reset) as desired.

Performs a global reset of device state machine logic. Terminates any ongoing 1-Wire

communication.

The command must be followed by a 1-Wire Reset Pulse command.

None

N/A

None

Maximum 1.635µs. Counted from rising SCL edge of the command code acknowledge

bit.

Ends maximum 1.09µs after the rising SCL edge of the command code acknowledge

bit.

(N/A)

RST set to 1; 1WB, PPD, SD, SBR, TSB, DIR set to 0.

1WS, APU, PDN, SPU set to 0.

tRSTL, tMSP, tW0L, tW1L, tREC0, and RWPU are reset to their default values.

1-Wire Reset Pulse

Command Code

Parameter Byte

Usage

Other Notes

Command Restrictions

Error Conditions (Error Response)

MAC Notes

I2C Busy Duration

Command Duration

1-Wire Activity

Read Pointer Position

Master Status Bits Affected

Master Configurations Affected

1-Wire Port Configurations Affected

B4h

N/A

To initiate or end any 1-Wire communication sequence. To finish a 1-Wire Master

Reset command.

Generates a 1-Wire reset/presence-detect cycle (Figure 5) at the 1-Wire line. The

state of the 1-Wire line is sampled at tSI and tMSP and the result is reported to the host

processor through the 1-Wire Master Status Register, bits PPD and SD.

1-Wire activity must have ended before the DS2465 can process this command.

Command code is not acknowledged if 1WB = 1 at the time the command code is

received and the command is ignored.

N/A

None

2 O tRSTL + maximum 1.09µs, counted from the rising SCL edge of the command

code acknowledge bit.

Begins maximum 1.09µs after the rising SCL edge of the command code

acknowledge bit.

1-Wire Master Status register (for busy polling).

1WB (set to 1 for 2 O tRSTL), PPD is updated at tRSTL + tMSP, SD is updated at tRSTL

+ tSI.

1WS and APU apply.

tRSTL, tMSP, and RWPU current values apply.

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