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DS2460 Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге
Компоненты Описание
производитель
DS2460
MaximIC
Maxim Integrated MaximIC
DS2460 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Abridged Data Sheet
DS2460
Slave Address
The slave address to which the DS2460 responds is shown in Figure 5. The logic states at the address pins AD0,
AD1 and AD2 determine the value of the address bits A0, A2, and A4. The address pins allow the device to
respond to one of eight possible slave addresses. The slave address is part of the slave-address/control byte. The
last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data will
flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access
mode).
Figure 4. I²C Protocol Overview
MS-bit
SDA
Slave Address
R/W ACK
bit
ACK
bit
Acknowledgment
from Receiver
Repeated if more bytes
are transferred
SCL
Idle START
Condition
12
6 78
9
ACK
12
Figure 5. DS2460 Slave Address
7-Bit Slave Address
89
ACK
A6 A5 A4 A3 A2 A1 A0
1 0 AD2 0 AD1 0 AD0 R/W
STOP Condition
Repeated START
Condition
Most Signi-
ficant Bit
AD2, AD1, AD0
Pin States
Determines
Read or Write
I²C Definitions
The following terminology is commonly used to describe I²C data transfers. The timing references are defined in
Figure 6.
Bus Idle or Not Busy
Both, SDA and SCL, are inactive and in their logic HIGH states.
START Condition
To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH. A valid slave address must be
sent by the master and acknowledged by the slave before subsequent START conditions are recognized.
STOP Condition
To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH. A valid slave address must be sent by the
master and acknowledged by the slave before subsequent STOP conditions are recognized.
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