DS2407 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2407

Dual Addressable Switch Plus 1K–Bit Memory

Dallas Semiconductor -> Maxim Integrated 

DS2407

If the CRC read by the bus master is incorrect, a Reset

Pulse must be issued and the entire sequence must be

repeated. If the CRC received by the bus master is cor-

rect, a programming pulse (12 volts on the 1–Wire bus

for 480 µs) is issued by the bus master. Prior to program-

ming, the entire unprogrammed EPROM memory field

will appear as logical 1s. For each bit in the data byte

provided by the bus master that is set to a logical 0, the

corresponding bit in the selected byte of the EPROM

memory is programmed to a logical 0 after the program-

ming pulse has been applied.

After the 480 µs programming pulse is applied and the

data line returns to the idle level (5 volts), the bus master

issues eight read time slots to verify that the appropriate

bits have been programmed. The DS2407 responds

with the data from the selected EPROM address sent

least significant bit first. This byte contains the bitwise

logical AND of all data ever written to this address. If the

EPROM byte contains 1s in bit positions where the byte

issued by the master contained 0s, a Reset Pulse

should be issued and the current byte address should

be programmed again. If the DS2407 EPROM byte con-

tains 0s in the same bit positions as the data byte, the

programming was successful and the DS2407 will auto-

matically increment its address counter to select the

next byte in the EPROM memory field. The new two–

byte address will also be loaded into the 16–bit CRC

generator as a starting value. The bus master will issue

the next byte of data using eight write time slots.

As the DS2407 receives this byte of data into the

scratchpad, it also shifts the data into the CRC genera-

tor that has been preloaded with the current address

and the result is a 16–bit CRC of the new data byte and

the new address. After supplying the data byte, the bus

master will read this 16–bit CRC from the DS2407 with

sixteen read time slots to confirm that the address

incremented properly and the data byte was received

correctly. If the CRC is incorrect, a Reset Pulse must be

issued and the write sequence must be restarted. If the

CRC is correct, the bus master will issue a programming

pulse and the selected byte in memory will be pro-

grammed.

Note that the initial pass through the write flow chart will

generate an 16–bit CRC value that is the result of shift-

ing the command byte into the CRC generator, followed

by the two address bytes, and finally the data byte. Sub-

sequent passes through the write flow chart due to the

DS2407 automatically incrementing its address counter

will generate a 16–bit CRC that is the result of loading

(not shifting) the new (incremented) address into the

CRC generator and then shifting in the new data byte.

For both of these cases, the decision to continue (to

apply a program pulse to the DS2407) is made entirely

by the bus master, since the DS2407 will not be able to

determine if the 16–bit CRC calculated by the bus mas-

ter agrees with the 16–bit CRC calculated by the

DS2407. If an incorrect CRC is ignored and a program

pulse is applied by the bus master, incorrect program-

ming could occur within the DS2407. Also note that the

DS2407 will always increment its internal address

counter after the receipt of the eight read time slots used

to confirm the programming of the selected EPROM

byte. The decision to continue is again made entirely by

the bus master. Therefore if the EPROM data byte does

not match the supplied data byte but the master contin-

ues with the write command, incorrect programming

could occur within the DS2407. The write command

sequence can be ended at any point by issuing a Reset

Pulse.

012099 10/31

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