DS2156 Просмотр технического описания (PDF) - Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Maxim Integrated 

DS2156

RCL, RLOS, RRA, and RAIS alarms interrupt on

Optional HEC insertion in transmit direction with

change-of-state

programmable COSET polynomial addition

Flexible signaling support

Option of using either idle or unassigned cells for

– Software or hardware based

cell-rate decoupling in transmit direction

– Interrupt generated on change of signaling data

1-Byte programmable pattern for payload of cells

– Receive signaling freeze on loss-of-sync,

used for cell-rate decoupling

carrier loss, or frame slip

Transmit FIFO depth configurable to either 2, 3, 4

Addition of hardware pins to indicate carrier loss

cell deep, which provides control over cell latency

and signaling freeze

Transmit FIFO depth indication for 2-cell space

Automatic RAI generation to ETS 300 011

specifications

Access to Sa and Si bits

Option to extend carrier loss criteria to a 1ms

period as per ETS 300 233

Japanese J1 support

– Ability to calculate and check CRC6 according

to the Japanese standard

– Ability to generate Yellow Alarm according to

the Japanese standard

Optional single-bit HEC error insertion

HEC-based cell delineation

Optional single-bit HEC error correction in the

receive direction

Optional filtering of HEC errored cells received

Optional receive idle/unassigned cell filtering

Programmable loss-of-cell delineation (LCD)

integration and optional interrupt

Interrupt for FIFO overrun in receive direction

Saturating counts for:

TDM Bus

Dual two-frame independent receive and transmit

elastic stores

– Independent control and clocking

– Controlled slip capability with status

– Minimum delay mode supported

– Number of error-free assigned cells received

and transmitted

– Number of correctable and uncorrectable HEC-

errored cells received

Optional internally generated clock (system clock

divided by 8) in diagnostic loopback mode

16.384MHz maximum backplane burst rate

Supports T1 to CEPT (E1) conversion

Programmable output clocks for fractional T1, E1,

H0, and H12 applications

Interleaving PCM bus operation

Hardware signaling capability

– Receive signaling reinsertion to a backplane

HDLC Controllers

Two independent HDLC controllers

Fast load and unload features for FIFOs

SS7 support for FISU transmit and receive

Independent 128-byte Rx and Tx buffers with

interrupt support

multiframe sync

Access FDL, Sa, or single/multiple DS0 channels

– Availability of signaling in a separate PCM

DS0 access includes Nx64 or Nx56

data stream

Compatible with polled or interrupt driven

– Signaling freezing

environments

Ability to pass the T1 F-bit position through the

Bit-oriented code (BOC) support

elastic stores in the 2.048MHz backplane mode

Access to the data streams in between the

framer/formatter and the elastic stores

User-selectable synthesized clock output

Test and Diagnostics

Programmable on-chip bit error-rate testing

Pseudorandom patterns including QRSS

UTOPIA Bus

Supports fractional T1/E1 and arbitrary bit rates in

multiples of 64kbps (DS0/TS) up to 2.048Mbps

User-defined repetitive patterns

Daly pattern

Error insertion single and continuous

Total bit and errored bit counts

Supports clear E1

Payload error insertion

Compliant to the ATM forum specifications for

Error insertion in the payload portion of the T1

ATM over DS1 and E1, respectively

frame in the transmit path

Standard UTOPIA-II interface to the ATM layer

Errors can be inserted over the entire frame or

Configurable UTOPIA address

selected channels

Supports diagnostic loopback

Optional payload scrambling in transmit direction

and descrambling in receive direction as per the

Insertion options include continuous and absolute

number with selectable insertion rates

F-bit corruption for line testing

ITU I.432 for the cell-based physical layer

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