DS2155DK Просмотр технического описания (PDF) - Maxim Integrated

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DS2155DK

T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards

Maxim Integrated 

CPLD Register Map

DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards

Table 2. CPLD Register Map

OFFSET

0X0000

0X0002

0X0003

0X0004

0X0005

0X0006

0X0007

0X0011

0X0012

0X0013

0X0014

0X0015

NAME

BID

XBIDH

XBIDM

XBIDL

BREV

AREV

PREV

SWITCH1

SWITCH2

SWITCH3

SWITCH4

LEVELS

TYPE

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Write

Read-Write

Read-Write

Read-Write

Read-Write

DESCRIPTION

Board ID

High-Nibble Extended Board ID

Middle-Nibble Extended Board ID

Low-Nibble Extended Board ID

Board FAB Revision

Board Assembly Revision

PLD Revision

Pin to 1.544MHz

Pin to 2.048MHz

Pin-to-Pin Connect

Pin-to-Pin Connect

Set Level On Pin 1 = 3.3V

ID Registers

OFFSET

0X0000

0X0002

0X0003

0X0004

NAME

BID

XBIDH

XBIDM

XBIDL

0X0005

BREV

0X0006

AREV

0X0007

PREV

TYPE

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

Read-Only

VALUE

DESCRIPTION

0xD

Board ID

0x0

High-Nibble Extended Board ID

0x0

Middle-Nibble Extended Board ID

0x5

Low-Nibble Extended Board ID

Displays current

FAB revision

Board FAB Revision

Displays current

assembly revision

Board Assembly Revision

Displays current

PLD firmware PLD Revision

revision

Control Registers

The control registers are used primarily to control several banks of FET switches that route clocks and backplane

signals. Please note that certain register settings cause line contention, e.g., setting SWITCH1.4 and SWITCH2.4

both to 0 would drive MCLK with both 1.544MHz and 2.048MHz.

SWITCH1: PIN TO 1.544MHz (OFFSET = 0x0011) INITIAL VALUE = 0xF

(MSB)

—

(LSB)

—

—

—

MCLK

TCLK RSYSCLK TSYSCLK

NAME

MCLK

TCLK

RSYSCLK

TSYSCLK

POSITION

SWITCH1.3

SWITCH1.2

SWITCH1.1

SWITCH1.0

FUNCTION

0 = Connect MCLK to the 1.544MHz clock

1 = Open Switch 1.4

0 = Connect TCLK to the 1.544MHz clock

1 = Open Switch 1.3

0 = Connect RSYSCLK to the 1.544MHz clock

1 = Open Switch 1.2

0 = Connect TSYSCLK to the 1.544MHz clock

1 = Open Switch 1.1

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