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DS21552 Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге
Компоненты Описание
производитель
DS21552
MaximIC
Maxim Integrated MaximIC
DS21552 Datasheet PDF : 137 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
3.2 DOCUMENT REVISION HISTORY
Revision
Notes
DS21352/DS21552
12-10-98
12-18-98
1-4-99
1-18-99
1-18-99
1-28-99
2-2-99
2-11-99
4-1-99
4-15-99
5-7-99
5-17-99
5-19-99
7-27-99
8-16-99
Initial Release
Add LIUODO (LIU Open Drain Output) to CCR7.0
Add CDIG (Customer Disconnect Indication Generator) to CCR7.1
Add LIUSI (Line Interface Unit Synchronization Interface) to CCR7.2
Correct IBO register bit functions order
Add bit level description to CCR3.6
Delete “The elastic stores can be forced to a known depth via the Elastic Store Reset bit (CCR3.6).
Toggling the CCR3.6 bit forces the read and write pointers into opposite frames” from section 12.0
Add receive IBO operation PCM timing diagram
Correct Device ID register bit definitions
Correct TSYSCLK and RSYSCLK AC timing and add 4.096 MHz and 8.192 MHz AC timing
Correct definition and label or TUDR bit in TPRM register
Correct format of register definitions in body of data sheet
Add Receive Monitor Mode section
Add section on Protected Interfaces
Correct FMS pin # and description in JTAG section
Correct name of status registers in section 15.3.2
Correct definition of RIR3.4
Correct Receive Monitor Mode section
Remove “Preliminary” notice from data sheet
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