DS21Q43A Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21Q43A

Quad E1 Framer

Dallas Semiconductor -> Maxim Integrated 

DS21Q43A BLOCK DIAGRAM Figure 1-1

DS21Q43A

READER’S NOTE

This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit

timeslots in an E1 system which are numbered 0 to 31. Timeslot 0 is transmitted first and received first.

These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is

identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made

up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is

the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:

FAS

Frame Alignment

CRC4

Cyclical Redundancy Check

CAS

Channel Associated

CCS

Common Channel Signaling

Signaling

MF

Multiframe

Sa

Additional bits

Si

International bits

E-bit

CRC4 Error bits

3 of 60

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