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DS21Q44 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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Компоненты Описание
производитель
DS21Q44
Dallas
Dallas Semiconductor -> Maxim Integrated Dallas
DS21Q44 Datasheet PDF : 105 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
DS21Q44
PIN
SYMBOL
TYPE DESCRIPTION
119
D2 or AD2
120
D3 or AD3
121
D4 or AD4
122
D5 or AD5
123
D6 or AD6
124
D7 or AD7
125
TSYSCLK0
126
TSER0
127
TSSYNC0
128
TSIG0
[TCHCLK0]
I/O Data Bus Bit or Address/Data Bit 2
I/O Data Bus Bit or Address/Data Bit 3
I/O Data Bus Bit or Address/Data Bit 4
I/O Data Bus Bit or Address/Data Bit 5
I/O Data Bus Bit or Address/Data Bit 6
I/O Data Bus Bit or Address/Data Bit 7; MSB
I Transmit System Clock for Elastic Store in Framer 0
I Transmit Serial Data for Framer 0
I Transmit Sync for Elastic Store in Framer 0
I Transmit Signaling Input for Framer 0
[O] [Transmit Channel Clock from Framer 0]
Note:
1. Brackets [ ] indicate pin function when the DS21Q44 is configured for emulation of the DS21Q43,
(FMS = 1).
Pin Description Sorted by Pin Function, FMS = 0 Table 2-2
PIN
SYMBOL
TYPE
DESCRIPTION
108
8MCLK
23
A0
24
A1
25
A2
26
A3
27
A4
28
A5
29
A6/ALE (AS)
46
A7
61
BTS
112
CLKSI
60
CS*
117
D0 or AD0
118
D1 or AD1
119
D2 or AD2
120
D3 or AD3
121
D4 or AD4
122
D5 or AD5
123
D6 or AD6
124
D7 or AD7
47
FMS
58
FS0
59
FS1
30
INT*
52
JTCLK
O 8 MHz Clock
I Address Bus Bit 0; LSB
I Address Bus Bit 1
I Address Bus Bit 2
I Address Bus Bit 3
I Address Bus Bit 4
I Address Bus Bit 5
I Address Bus Bit 6; MSB or Address Latch Enable (Address
Strobe)
I Address Bus Bit 7
I Bus Type Select for Parallel Control Port
I 8MCLK Clock Reference Input
I Chip Select
I/O Data Bus Bit or Address/Data Bit 0; LSB
I/O Data Bus Bit or Address/Data Bit 1
I/O Data Bus Bit or Address/Data Bit 2
I/O Data Bus Bit or Address/Data Bit 3
I/O Data Bus Bit or Address/Data Bit 4
I/O Data Bus Bit or Address/Data Bit 5
I/O Data Bus Bit or Address/Data Bit 6
I/O Data Bus Bit or Address/Data Bit 7; MSB
I Framer Mode Select
I Framer Select 0 for Parallel Control Port
I Framer Select 1 for Parallel Control Port
O Receive Alarm Interrupt for all Four Framers
I JTAG Test Clock
10 of 105

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