DS21Q42 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS21Q42 Datasheet PDF : 119 Pages
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TABLE OF CONTENTS
DS21Q42
1. INTRODUCTION .............................................................................................................................. 2
2. DS21Q42 PIN DESCRIPTION ......................................................................................................... 8
3. DS21Q42 PIN FUNCTION DESCRIPTION ................................................................................ 15
4. DS21Q42 REGISTER MAP............................................................................................................. 22
5. PARALLEL PORT........................................................................................................................... 26
6. CONTROL, ID AND TEST REGISTERS ..................................................................................... 26
7. STATUS AND INFORMATION REGISTERS............................................................................. 37
8. ERROR COUNT REGISTERS....................................................................................................... 45
9. DS0 MONITORING FUNCTION................................................................................................... 48
10. SIGNALING OPERATION ............................................................................................................ 50
10.1. PROCESSOR BASED SIGNALING ................................................................................... 50
10.2. HARDWARE BASED SIGNALING ................................................................................... 52
11. PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK....................................... 53
11.1. TRANSMIT SIDE CODE GENERATION ............................................................................ 53
11.1.1. Simple Idle Code Insertion and Per–Channel Loopback ................................................. 54
11.1.2. Per–Channel Code Insertion ........................................................................................... .55
11.2. RECEIVE SIDE CODE GENERATION ................................................................................ 55
11.2.1. Simple Code Insertion .................................................................................................... 55
11.2.2. Per–Channel Code Insertion ............................................................................................. 56
12. CLOCK BLOCKING REGISTERS .............................................................................................. 57
13. ELASTIC STORES OPERATION .............................................................................................. 58
13.1. RECEIVE SIDE ....................................................................................................................... 58
13.2. TRANSMIT SIDE ................................................................................................................... 58
13.3. MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE .............................. 59
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