DS21455 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS21455 Datasheet PDF : 270 Pages
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
13. I/O PIN CONFIGURATION OPTIONS ..........................................................................................................78
14. LOOPBACK CONFIGURATIONS ................................................................................................................80
14.1 PER-CHANNEL PAYLOAD LOOPBACK .................................................................................. 83
15. ERROR COUNT REGISTERS......................................................................................................................85
15.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) ............................................................ 86
15.1.1 T1 Operation....................................................................................................................86
15.1.2 E1 Operation....................................................................................................................86
15.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) .......................................................... 88
15.2.1 T1 Operation....................................................................................................................88
15.2.2 E1 Operation....................................................................................................................88
15.3 FRAMES OUT OF SYNC COUNT REGISTER (FOSCR) .......................................................... 89
15.3.1 T1 Operation....................................................................................................................89
15.3.2 E1 Operation....................................................................................................................89
15.4 E-BIT COUNTER REGISTER (EBCR)................................................................................... 90
16. DS0 MONITORING FUNCTION ...................................................................................................................91
16.1 TRANSMIT DS0 MONITOR REGISTERS ................................................................................ 91
16.2 RECEIVE DS0 MONITOR REGISTERS .................................................................................. 92
17. SIGNALING OPERATION ............................................................................................................................93
17.1 RECEIVE SIGNALING .......................................................................................................... 93
17.1.1 Processor-Based Receive Signaling............................................................................94
17.1.2 Hardware-Based Receive Signaling ............................................................................94
17.2 TRANSMIT SIGNALING ...................................................................................................... 100
17.2.1 Processor-Based Transmit Signaling ........................................................................100
17.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode.............................104
17.2.3 Software Signaling Insertion Enable Registers, T1 Mode ......................................106
18. PER-CHANNEL IDLE CODE GENERATION ............................................................................................108
18.1 IDLE CODE PROGRAMMING EXAMPLES ............................................................................. 109
19. CHANNEL BLOCKING REGISTERS.........................................................................................................113
20. ELASTIC STORES OPERATION...............................................................................................................116
20.1 RECEIVE SIDE ................................................................................................................. 119
20.1.1 T1 Mode .........................................................................................................................119
20.1.2 E1 Mode .........................................................................................................................119
20.2 TRANSMIT SIDE ............................................................................................................... 120
20.2.1 T1 Mode .........................................................................................................................120
20.2.2 E1 Mode .........................................................................................................................120
20.3 ELASTIC STORES INITIALIZATION ...................................................................................... 120
20.4 MINIMUM-DELAY MODE ................................................................................................... 121
21. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................................122
22. T1 BIT ORIENTED CODE (BOC) CONTROLLER.....................................................................................123
22.1 TRANSMIT BOC............................................................................................................... 123
22.2 RECEIVE BOC................................................................................................................. 123
23. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) ........................................127
23.1 HARDWARE SCHEME (METHOD 1) .................................................................................... 127
23.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME (METHOD 2) ............................. 127
23.3 INTERNAL REGISTER SCHEME BASED ON CRC-4 MULTIFRAME (METHOD 3)...................... 130
24. HDLC CONTROLLERS ..............................................................................................................................141
24.1 BASIC OPERATION DETAILS ............................................................................................. 141
24.2 HDLC CONFIGURATION................................................................................................... 143
24.2.1 FIFO Control ..................................................................................................................145
24.3 HDLC MAPPING.............................................................................................................. 146
24.3.1 Receive...........................................................................................................................146
24.3.2 Transmit .........................................................................................................................148
24.3.3 FIFO Information ...........................................................................................................153
24.3.4 Receive Packet Bytes Available .................................................................................153
24.3.5 HDLC FIFOS .................................................................................................................154
24.4 RECEIVE HDLC CODE EXAMPLE...................................................................................... 155
24.5 LEGACY FDL SUPPORT (T1 MODE) ................................................................................. 155
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