DS21455 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS21455 Datasheet PDF : 270 Pages
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
TABLE OF CONTENTS
1. DESCRIPTION ................................................................................................................................................9
1.1 STANDARDS ...................................................................................................................... 10
2. FEATURE HIGHLIGHTS...............................................................................................................................11
2.1 GENERAL .......................................................................................................................... 11
2.2 LINE INTERFACE ................................................................................................................ 11
2.3 CLOCK SYNTHESIZER ........................................................................................................ 11
2.4 JITTER ATTENUATOR ......................................................................................................... 12
2.5 FRAMER/FORMATTER ........................................................................................................ 12
2.6 SYSTEM INTERFACE........................................................................................................... 13
2.7 HDLC CONTROLLERS ....................................................................................................... 13
2.8 TEST AND DIAGNOSTICS .................................................................................................... 13
2.9 EXTENDED SYSTEM INFORMATION BUS .............................................................................. 14
2.10 CONTROL PORT ................................................................................................................ 14
3. BLOCK DIAGRAM ........................................................................................................................................15
4. DS21455/DS21458 DELTA ...........................................................................................................................17
4.1 PACKAGE .......................................................................................................................... 17
4.2 CONTROLLER INTERFACE................................................................................................... 17
4.3 ESIB FUNCTION................................................................................................................ 17
4.4 FRAMER/LIU INTERIM SIGNALS .......................................................................................... 17
5. PIN FUNCTION DESCRIPTION....................................................................................................................20
5.1 TRANSMIT SIDE PINS ......................................................................................................... 20
5.2 RECEIVE SIDE PINS ........................................................................................................... 22
5.3 PARALLEL CONTROL PORT PINS ........................................................................................ 24
5.4 EXTENDED SYSTEM INFORMATION BUS .............................................................................. 26
5.5 JTAG TEST ACCESS PORT PINS........................................................................................ 26
5.6 LINE INTERFACE PINS ........................................................................................................ 27
5.7 SUPPLY PINS .................................................................................................................... 28
5.8 PIN DESCRIPTIONS ............................................................................................................ 29
5.9 PACKAGES ........................................................................................................................ 39
6. PARALLEL PORT .........................................................................................................................................41
6.1 REGISTER MAP ................................................................................................................. 41
7. SPECIAL PER-CHANNEL REGISTER OPERATION ..................................................................................46
8. PROGRAMMING MODEL.............................................................................................................................48
8.1 POWER-UP SEQUENCE...................................................................................................... 49
8.1.1 Master Mode Register........................................................................................................49
8.2 INTERRUPT HANDLING ....................................................................................................... 50
8.3 STATUS REGISTERS .......................................................................................................... 50
8.4 INFORMATION REGISTERS.................................................................................................. 51
8.5 INTERRUPT INFORMATION REGISTERS ................................................................................ 51
9. CLOCK MAP .................................................................................................................................................52
10. T1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................53
10.1 T1 CONTROL REGISTERS .................................................................................................. 53
10.2 T1 TRANSMIT TRANSPARENCY........................................................................................... 58
10.3 AIS-CI AND RAI-CI GENERATION AND DETECTION ............................................................. 59
10.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION ................................................. 60
10.5 T1 INFORMATION REGISTER............................................................................................... 62
11. E1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................64
11.1 E1 CONTROL REGISTERS .................................................................................................. 64
11.2 AUTOMATIC ALARM GENERATION ....................................................................................... 68
11.2.1 Auto AIS ...........................................................................................................................68
11.2.2 Auto RAI ...........................................................................................................................68
11.2.3 Auto E-Bit .........................................................................................................................68
11.2.4 G.706 CRC-4 Interworking ............................................................................................68
11.3 E1 INFORMATION REGISTERS ............................................................................................ 69
12. COMMON CONTROL AND STATUS REGISTERS.....................................................................................71
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