DS21455 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

DS21455

Quad T1/E1/J1 Transceivers

Dallas Semiconductor -> Maxim Integrated 

DS21455/DS21458 Quad T1/E1/J1 Transceivers

4. DS21455/DS21458 DELTA

This section describes the differences between the DS21455 and DS21458.

4.1 Package

DS21455: 27mm, 256-pin, 1.27 ball pitch, BGA (This package has the same footprint and pinout as the

DS21Q55.)

DS21458: 17mm, 256-pin, 1.00 ball pitch, CSBGA

4.2 Controller Interface

DS21455: The CPU interface has 8 address lines with independent chip selects (4) per transceiver.

DS21458: The CPU interface has 10 address lines with a single chip select. The upper address lines, A8

and A9, act as coded transceiver selects.

4.3 ESIB Function

The ESIB function provides a fast method of determining interrupt and alarm status when multiple ports

(up to 8) are being controlled by a single processor.

DS21455: The three ESIB signals are brought out for each transceiver. The user must externally

configure the ESIB group.

DS21458: The ESIB signals are internally bused and only a single set of signals are brought out to enable

the connection of another DS21458 into an 8-port ESIB.

4.4 Framer/LIU Interim Signals

Access to the clock and bipolar data signals between the framer and LIU function may be used for

specialized applications. An internal MUX connects the framer and LIU if these signals are unused. The

MUX is controlled via the LIUC/TPD pin and LIUC bit in the LBCR register. The unused inputs must be

connected to ground.

DS21455: The user has access to all clock and data signals between the framer and LIU on all

transceivers as shown in Figure 4-1.

DS21458: The user has limited access to clock and data signals between the framer and LIU on all

transceivers as shown in Figure 4-2.

17 of 270

Share Link: