DS21455 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS21455 Datasheet PDF : 270 Pages
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 3-2. DS21455 Block Diagram
MCLK1 MCLK2
RTIP
RRING
TTIP
TRING
LIUC/TPD
TRANSCEIVER #4
TRANSCEIVER #3
TRANSCEIVER #2
8XCLK
MASTER
CLOCK
RPOSO RPOSI
RNEGO RNEGI
RCLKO RCLKI
2 HDLCs BERT
BACKPLANE
CLOCK
RECEIVE
LIU
CLOCK & DATA
RECOVERY
JITTER
ATTEN.
TRANSMIT
LIU
WAVESHAPE
GENERATION
TRANSMIT
OR RECEIVE
PATH
JITTER
ATTEN.
MUX
RECEIVE
FRAMER
SYNCHRONIZATION
ALARM MONITORING
SIGNALING EXTRACTION
HDLC EXTRACTION
DS0 CONDITIONING
HDB3/B8ZS DECODER
DS21455
TRANSMIT
FRAMER
MUX
FRAMING
CRC RECALCULAION(E1)
ALARM INSERTION
SIGNALING INSERTION
HDLC INSERTION
DS0 CONDITIONING
HDB3/B8ZS CODER
RECEIVE
BACKPLANE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
TRTARNANSSMMIIT
BACBAKCPKLPALANNEE
INTINETREFRAFACCEE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
2 HDLCs BERT
BPCLK
RSYSCLK
RCLK
RSER
RSIG
RSIGF
RSYNC
RFSYNC
RMSYNC
RCHCLK
RCHBLK
RLCLK
RLINK
TSYSCLK
TCLK
TSER
TSIG
TSYNC
TSSYNC
TCHCLK
TCHBLK
TLCLK
TLINK
RLOS/LOTC
JTAG
ESIB
TPOSI TPOSOI
TNEGI TNEGO
TCLKI TCLKO
CPU INTERFACE
MUX/NON-MUX, INTEL/MOTOROLA
JTDO JTCLK JTMS ESIBS0 ESIBRD
JTDI JTRST
ESIBS1
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