DS21372TN Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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производитель

DS21372TN

3.3V Bit Error Rate Tester (BERT)

Dallas Semiconductor -> Maxim Integrated 

7. ERROR INSERT REGISTER

DS21372

The Error Insertion Register (EIR) controls circuitry within the DS21372 that allows the generated

pattern to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by

properly programming the EIR0 to EIR2 bits or bit errors can be inserted at random (under

microcontroller control) via the EIR.3 bit.

EIR: ERROR INSERT REGISTER (ADDRESS=07 HEX)

(MSB)

(LSB)

-

-

TINV

RINV

SBE

EIR2

EIR1

EIR0

SYMBOL

-

-

TINV

RINV

SBE

EIB2

EIB1

EIB0

POSITION

EIR.7

EIR.6

EIR.5

EIR.4

EIR.3

EIR.2

EIR.1

EIR.0

NAME AND DESCRIPTION

Not Assigned. Should be set to 0 when written to.

Not Assigned. Should be set to 0 when written to.

Transmit Data Inversion Select.

0 = do not invert data to be transmitted at TDATA

1 = invert data to be transmitted at TDATA

Receive Data Inversion Select.

0 = do not invert data received at RDATA

1 = invert data received at RDATA

Single Bit Error Insert. A low to high transition will create a

single bit error. Must be cleared and set again for a subsequent

bit error to be inserted. Can be used to accomplish rates not

addressed in Table 3 (e.g., BER of less than 10-7).

Error Insert Bit 2. See Table 3.

Error Insert Bit 1. See Table 3.

Error Insert Bit 0. See Table 3.

ERROR BIT INSERTION Table 3

EIB2

EIB1

EIB0

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

9 of 21

ERROR RATE INSERTED

no errors automatically inserted

10-1

10-2

10-3

10-4

10-5

10-6

10-7

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