DS21372TN Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS21372TN Datasheet PDF : 21 Pages
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REPETITIVE PATTERN GENERATION (PCR.5=0) Table 5
PATTERN TYPE
PTR PLR PSR3 PSR2 PSR1
all 1s
00 00 FF FF FF
all 0s
00 00 FF FF FF
alternating 1s and 0s
00 01 FF FF FF
double alternating 1s and 0s
00 03 FF FF FF
3 in 24
00 17 FF 20 00
1 in 16
00 0F FF FF 00
1 in 8
00 07 FF FF FF
1 in 4
00 03 FF FF FF
D4 Line Loopback Activate
00 04 FF FF FF
D4 Line Loopback Deactivate
00 02 FF FF FF
PSR0
FF
FE
FE
FC
22
01
01
F1
F0
FC
DS21372
TINV
0
0
0
0
0
0
0
0
0
0
RINV
0
0
0
0
0
0
0
0
0
0
Notes For Tables 4 And 5:
1. PTR = Polynomial Tap Register (address = 05)
2. PLR = Pattern Length Register (address = 04)
3. PSR3 = Pattern Set Register 3 (address = 00)
4. PSR2 = Pattern Set Register 2 (address = 01)
5. PSR1 = Pattern Set Register 1 (address = 02)
6. PSR0 = Pattern Set Register 0 (address = 03)
7. TINV = Transmit Data Inversion Select Bit (EIR.5)
8. RINV = Receive Data Inversion Select Bit (EIR.4)
9. For the 232 -1 pattern, the random pattern actually repeats every (4093 x 220) + 1046529 bits instead of
232 - 1.
8. BIT COUNT REGISTERS
The Bit Count Registers (BCR3 to BCR0) comprise a 32-bit count of bits (actually RCLK cycles)
received at RDATA. BC31 is the MSB of the 32-bit count. The bit counter increments for each cycle of
RCLK when input pin RDIS is low. The bit counter is disabled during loss of SYNC. The Status Register
bit BCOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the
BCR by either toggling the LC bit or pin. The DS21372 latches the bit count into the BCR registers and
clears the internal bit count when either the PCR.4 bit or the LC input pin toggles from low to high. The
bit count and bit error count (available via the BECRs) are used by an external processor to compute the
BER performance on a loop or channel basis.
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