DS21554 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21554

DS21354 (3.3V) and DS21554 (5V) E1 Single Chip Transceivers (SCT)

Dallas Semiconductor -> Maxim Integrated 

3.2 DOCUMENT REVISION HISTORY

DS21354 & DS21554

Date

Notes

1-27-99

1-28-99

2-3-99

2-11-99

4-1-99

4-15-99

5-7-99

7-29-99

9-14-99

9-23-99

Initial release

Corrected TSYSCLK and RSYSCLK timing and added 4.096 MHz and 8.192 MHz

timing

Corrected definition and label of TUDR bit in the THIR register.

Correct address of IBO register in text.

Add Receive Monitor Mode section

Add section on Protected Interfaces

Correct pin # and description of FMS in JTAG section

Add list of tables and figures

Add 10uf cap to interface examples

Correct definition of DS* in pin description.

9 of 117

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