DS21554L Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

DS21554L

DS21354 (3.3V) and DS21554 (5V) E1 Single Chip Transceivers (SCT)

Dallas Semiconductor -> Maxim Integrated 

DS21354 & DS21554

3.1 Functional Description

The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP

pins of the DS21354/554. The device recovers clock and data from the analog signal and passes it

through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to

locate the framing/multi-frame pattern. The DS21354/554 contains an active filter that reconstructs the

analog received signal for the nonlinear losses that occur in transmission. The device has a usable receive

sensitivity of 0 dB to –43 dB which allows the device to operate on cables over 2km in length. The

receive side framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects

incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If needed, the

receive side elastic store can be enabled in order to absorb the phase and frequency differences between

the recovered E1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK

input. The clock applied at the RSYSCLK input can be either a 2.048/4.096/8.192 MHz clock or a 1.544

MHz clock.

The transmit side framer is totally independent from the receive side in both the clock requirements and

characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary.

The transmit formatter will provide the necessary frame/multiframe data overhead for E1 transmission.

Reader’s Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In

each 125 us frame, there are 32 eight–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and

received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32.

Timeslot 0 is identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or

channel) is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted

first. Bit number 8 is the LSB and is transmitted last. The term “locked” is used to refer to two clock

signals that are phase or frequency locked or derived from a common clock (i.e., a 1.544MHz clock may

be locked to a 2.048MHz clock if they share the same 8KHz component). Throughout this data sheet, the

following abbreviations will be used:

FAS

CAS

MF

Si

CRC4

CCS

Sa

E-bit

Frame Alignment Signal

Channel Associated Signaling

Multiframe

International bits

Cyclical Redundancy Check

Common Channel Signaling

Additional bits

CRC4 Error Bits

8 of 117

Share Link: