DS21554 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21554

DS21354 (3.3V) and DS21554 (5V) E1 Single Chip Transceivers (SCT)

Dallas Semiconductor -> Maxim Integrated 

DS21354 & DS21554

3 INTRODUCTION

The DS21354/554 is a superset version of the popular DS2153 and DS2154 SCTs offering the new

features listed below. All of the original features of the DS2153 and DS2154 have been retained and

software created for the original devices is transferable into the DS21354/554.

New Features in the DS21354 and DS21554

FEATURE

HDLC controller with 64-byte buffers for Sa bits or DS0s or sub DS0s

Interleaving PCM bus operation

IEEE 1149.1 JTAG-Boundary Scan Architecture

3.3V (DS21354 only) supply

Line Interface Support for the G.703 2.048 Synchronization Interface

Customer Disconnect Indication (...101010...) Generator

Open Drain Line Driver Option

SECTION

15

18

17

2 and 3

16

6

16

New Features in the DS2154 (also in the DS21354 and DS21554)

FEATURE

SECTION

Option for non–multiplexed bus operation

1 and 2

Crystal–less jitter attenuation

12

Additional hardware signaling capability including:

7

Receive signaling reinsertion to a backplane multiframe sync

Availability of signaling in a separate PCM data stream

Signaling freezing Interrupt generated on change of signaling data

Improved receive sensitivity: 0 dB to –43 dB

12

Per–channel code insertion in both transmit and receive paths

8

Expanded access to Sa and Si bits

11

RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state

4

8.192 MHz clock synthesizer

1

Per–channel loopback

8

Addition of hardware pins to indicate carrier loss and signaling freeze

1

Line interface function can be completely decoupled from the framer/formatter to

1

allow:

Interface to optical, HDSL, and other NRZ interfaces

“tap” the transmit and receive bipolar data streams for monitoring purposes

Be able to corrupt data and insert framing errors, CRC errors, etc.

Transmit and receive elastic stores now have independent backplane clocks

1

Ability to monitor one DS0 channel in both the transmit and receive paths

6

Access to the data streams in between the framer/formatter and the elastic stores

1

AIS generation in the line interface that is independent of loopbacks

1 and 3

Transmit current limiter to meet the 50 mA short circuit requirement

12

Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233

3

Automatic RAI generation to ETS 300 011 specifications

3

7 of 117

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