DS21554 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21554

DS21354 (3.3V) and DS21554 (5V) E1 Single Chip Transceivers (SCT)

Dallas Semiconductor -> Maxim Integrated 

DS21354 & DS21554

1 LIST OF FIGURES

Figure 3-1

DS2135/554 BLOCK DIAGRAM.................................................................................10

Figure 16-1 BASIC EXTERNAL ANALOG CONNECTIONS.......................................................71

Figure 16-2 OPTIONAL CRYSTAL CONNECTION......................................................................72

Figure 16-3 JITTER TOLERANCE ..................................................................................................72

Figure 16-4 JITTER ATTENUATION .............................................................................................73

Figure 16-5 TRANSMIT WAVEFORM TEMPLATE .....................................................................73

Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21554 ....................................74

Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR THE DS21354 ....................................75

Figure 16-8 TYPICAL MONITOR PORT APPLICATION.............................................................76

Figure 17-1 JTAG FUNCTIONAL BLOCK DIAGRAM.................................................................78

Figure 17-2 TAP CONTROLLER STATE DIAGRAM ...................................................................81

Figure 18-1 IBO BASIC CONFIGURATION USING 4 SCTS .......................................................87

Figure 19-1 RECEIVE SIDE TIMING..............................................................................................88

Figure 19-2 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled).........................89

Figure 19-3 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) ......90

Figure 19-4 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) .....91

Figure 19-5 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE .........................92

Figure 19-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE ......................93

Figure 19-7 TRANSMIT SIDE TIMING ..........................................................................................94

Figure 19-8 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) .....................95

Figure 19-9 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)..........96

Figure 19-10 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)..........97

Figure 19-11 TRANSMIT SIDE INTERLEAVE BUS OPERATIONS, BYTE MODE....................98

Figure 19-12 TRANSMIT SIDE INTERLEAVE BUS OPERATIONS, FRAME MODE ................99

Figure 19-13 G.802 TIMING ............................................................................................................100

Figure 19-14 DS21354/554 FRAMER SYNCHRONIZATION FLOWCHART .............................101

Figure 19-15 DS21354/554 TRANSMIT DATA FLOW..................................................................102

Figure 21-1 INTEL BUS READ AC TIMING (BTS=0 / MUX=1)................................................105

Figure 21-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ...................................................105

Figure 21-3 MOTOROLA BUS AC TIMING (BTS=1 / MUX=1) ................................................106

Figure 21-4 INTEL BUS READ AC TIMING (BTS=0 / MUX=0)................................................108

Figure 21-5 INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0)..............................................108

Figure 21-6 MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0).....................................109

Figure 21-7 MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0)...................................109

Figure 21-8 RECEIVE SIDE AC TIMING .....................................................................................111

Figure 21-9 RECEIVE SYSTEM SIDE AC TIMING ....................................................................112

Figure 21-10 RECEIVE LINE INTERFACE AC TIMING..............................................................113

Figure 21-11 TRANSMIT SIDE AC TIMING .................................................................................115

Figure 21-12 TRANSMIT SYSTEM SIDE AC TIMING.................................................................116

Figure 21-13 TRANSMIT LINE INTERFACE SIDE AC TIMING ................................................116

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