DS21348 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21348

3.3V E1/T1/J1 Line Interface

Dallas Semiconductor -> Maxim Integrated 

1. LIST OF FIGURES

DS21348/Q348

Figure 3-1 DS21348 BLOCK DIAGRAM................................................................................................... 7

Figure 3-2 RECEIVE LOGIC....................................................................................................................... 8

Figure 3-3 TRANSMIT LOGIC ................................................................................................................... 9

Figure 4-1 PARALLEL PORT MODE PINOUT (BIS1 = 0, BIS0 = 1 or 0)............................................. 22

Figure 4-2 SERIAL PORT MODE PINOUT (BIS1 = 1, BIS0 = 0) .......................................................... 22

Figure 4-3 HARDWARE MODE PINOUT (BIS1 = 1, BIS0 = 1) ............................................................ 22

Figure 5-1 SERIAL PORT OPERATION FOR READ ACCESS (R=1) MODE 1.................................. 25

Figure 5-2 SERIAL PORT OPERATION FOR READ ACCESS MODE 2 ............................................. 25

Figure 5-3 SERIAL PORT OPERATION FOR READ ACCESS MODE 3 ............................................. 26

Figure 5-4 SERIAL PORT OPERATION FOR READ ACCESS MODE 4 ............................................. 26

Figure 5-5 SERIAL PORT OPERATION FOR WRITE ACCESS (R=0) MODES 1&2 ...……………27

Figure 5-6 SERIAL PORT OPERATION FOR WRITE ACCESS MODES 3& 4 …………...…………27

Figure 9-1 BASIC INTERFACE…………………………………………………………………………49

Figure 9-2 PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION.................... 50

Figure 9-3 PROTECTED INTERFACE USING EXTERNAL RECEIVE TERMINATION................... 51

Figure 9-4 E1 TRANSMIT PULSE TEMPLATE...................................................................................... 52

Figure 9-5 T1 TRANSMIT PULSE TEMPLATE...................................................................................... 53

Figure 9-6 JITTER TOLERANCE ............................................................................................................. 54

Figure 9-7 JITTER ATTENUATION ........................................................................................................ 54

Figure 10-1 BGA 12 x 12 PIN LAYOUT .................................................................................................. 58

Figure 12-1 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0)............................................. 62

Figure 12-2 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 0)........................................... 62

Figure 12-3 MOTOROLA BUS TIMING (PBTS = 1, BIS1 = 0, BIS0 = 0) ............................................ 63

Figure 12-4 INTEL BUS READ TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1)............................................. 65

Figure 12-5 INTEL BUS WRITE TIMING (PBTS = 0, BIS1 = 0, BIS0 = 1)........................................... 65

Figure 12-6 MOTOROLA BUS READ TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................. 66

Figure 12-7 MOTOROLA BUS WRITE TIMING (PBTS = 1, BIS1 = 0, BIS0 = 1)................................ 66

Figure 12-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0)........................................................................ 67

Figure 12-9 RECEIVE SIDE TIMING ...................................................................................................... 68

Figure 12-10 TRANSMIT SIDE TIMING................................................................................................. 69

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