DS2156 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Dallas Semiconductor -> Maxim Integrated 

DS2156

FIGURE 34-1. RECEIVE-SIDE D4 TIMING ..............................................................................................................233

FIGURE 34-2. RECEIVE-SIDE ESF TIMING ............................................................................................................233

FIGURE 34-3. RECEIVE-SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED)..........................................234

FIGURE 34-4. RECEIVE-SIDE 1.544MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED).......................234

FIGURE 34-5. RECEIVE-SIDE 2.048MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED).......................235

FIGURE 34-6. TRANSMIT SIDE D4 TIMING............................................................................................................235

FIGURE 34-7. TRANSMIT-SIDE ESF TIMING..........................................................................................................236

FIGURE 34-8. TRANSMIT-SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED) .....................................236

FIGURE 34-9. TRANSMIT-SIDE 1.544MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) ....................237

FIGURE 34-10. TRANSMIT-SIDE 2.048MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) ..................237

34.2 E1 MODE .................................................................................................................................................238

FIGURE 34-11. RECEIVE-SIDE TIMING............................................................................................................238

FIGURE 34-12. RECEIVE-SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED)........................................238

FIGURE 34-13. RECEIVE-SIDE BOUNDARY TIMING, RSYSCLK = 1.544MHZ (ELASTIC STORE ENABLED) .......239

FIGURE 34-14. RECEIVE-SIDE BOUNDARY TIMING, RSYSCLK = 2.048MHZ (ELASTIC STORE ENABLED) .......239

FIGURE 34-15. RECEIVE IBO CHANNEL INTERLEAVE MODE TIMING..................................................................240

FIGURE 34-16. RECEIVE IBO FRAME INTERLEAVE MODE TIMING ......................................................................241

FIGURE 34-17. G.802 TIMING, E1 MODE ONLY ...................................................................................................242

FIGURE 34-18. TRANSMIT-SIDE TIMING ...............................................................................................................242

FIGURE 34-19. TRANSMIT-SIDE BOUNDARY TIMING (ELASTIC STORE DISABLED) .............................................243

FIGURE 34-20. TRANSMIT-SIDE BOUNDARY TIMING, TSYSCLK = 1.544MHZ (ELASTIC STORE ENABLED) ....243

FIGURE 34-22. TRANSMIT IBO CHANNEL INTERLEAVE MODE TIMING...............................................................245

FIGURE 34-23. TRANSMIT IBO FRAME INTERLEAVE MODE TIMING ...................................................................246

35. OPERATING PARAMETERS ................................................................................................................247

36. AC TIMING PARAMETERS AND DIAGRAMS .................................................................................249

36.1 MULTIPLEXED BUS AC CHARACTERISTICS ............................................................................................249

FIGURE 36-1. INTEL BUS READ TIMING (BTS = 0/MUX = 1) ..............................................................................250

FIGURE 36-2. INTEL BUS WRITE TIMING (BTS = 0/MUX = 1) ............................................................................250

FIGURE 36-3. MOTOROLA BUS TIMING (BTS = 1/MUX = 1)...............................................................................251

36.2 NONMULTIPLEXED BUS AC CHARACTERISTICS .....................................................................................252

FIGURE 36-4. INTEL BUS READ TIMING (BTS = 0/MUX = 0) ..............................................................................253

FIGURE 36-5. INTEL BUS WRITE TIMING (BTS = 0/MUX = 0) ............................................................................253

FIGURE 36-6. MOTOROLA BUS READ TIMING (BTS = 1/MUX = 0).....................................................................254

FIGURE 36-7. MOTOROLA BUS WRITE TIMING (BTS = 1/MUX = 0)...................................................................254

36.3 RECEIVE-SIDE AC CHARACTERISTICS ....................................................................................................255

FIGURE 36-9. RECEIVE-SIDE TIMING, ELASTIC STORE ENABLED ........................................................................257

FIGURE 36-10. RECEIVE LINE INTERFACE TIMING ...............................................................................................257

36.4 TRANSMIT AC CHARACTERISTICS ..........................................................................................................258

FIGURE 36-11. TRANSMIT-SIDE TIMING ...............................................................................................................259

FIGURE 36-12. TRANSMIT-SIDE TIMING, ELASTIC STORE ENABLED....................................................................260

FIGURE 36-13. TRANSMIT LINE INTERFACE TIMING ............................................................................................260

36.5 UTOPIA TRANSMIT AC CHARACTERISTICS ..........................................................................................261

36.6 UTOPIA RECEIVE AC CHARACTERISTICS .............................................................................................261

FIGURE 36-14. UTOPIA INTERFACE SETUP AND HOLD TIMES............................................................................261

FIGURE 36-15. UTOPIA INTERFACE DELAY TIMES .............................................................................................261

37. MECHANICAL DESCRIPTION ............................................................................................................262

37.1 LQFP (L) PACKAGE ................................................................................................................................262

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