DS2156 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Dallas Semiconductor -> Maxim Integrated 

DS2156

26. BERT FUNCTION....................................................................................................................................200

26.1 STATUS ....................................................................................................................................................200

26.2 MAPPING .................................................................................................................................................200

FIGURE 26-1. SIMPLIFIED DIAGRAM OF BERT IN NETWORK DIRECTION ............................................................201

FIGURE 26-2. SIMPLIFIED DIAGRAM OF BERT IN BACKPLANE DIRECTION.........................................................201

26.3 BERT REGISTER DESCRIPTIONS .............................................................................................................202

26.4 BERT REPETITIVE PATTERN SET............................................................................................................206

26.5 BERT BIT COUNTER ...............................................................................................................................207

26.6 BERT ERROR COUNTER .........................................................................................................................208

27. PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)..................................................210

TABLE 27-A. TRANSMIT ERROR-INSERTION SETUP SEQUENCE ...........................................................................210

27.1 NUMBER-OF-ERRORS REGISTERS............................................................................................................212

TABLE 27-B. ERROR INSERTION EXAMPLES.........................................................................................................212

27.1.1 Number-of-Errors Left Register..........................................................................................................213

28. INTERLEAVED PCM BUS OPERATION (IBO).................................................................................214

28.1 CHANNEL INTERLEAVE ...........................................................................................................................214

28.2 FRAME INTERLEAVE................................................................................................................................214

FIGURE 28-1. IBO EXAMPLE ................................................................................................................................216

29. EXTENDED SYSTEM INFORMATION BUS (ESIB) .........................................................................217

FIGURE 29-1. ESIB GROUP OF FOUR DS2156S ....................................................................................................217

30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER ..........................................................221

31. FRACTIONAL T1/E1 SUPPORT ...........................................................................................................221

31.1 TDM BACKPLANE MODE........................................................................................................................221

31.2 UTOPIA BACKPLANE MODE ..................................................................................................................222

32. USER-PROGRAMMABLE OUTPUT PINS..........................................................................................223

33. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................................224

33.1 DESCRIPTION ...........................................................................................................................................224

FIGURE 33-1. JTAG FUNCTIONAL BLOCK DIAGRAM ...........................................................................................224

FIGURE 33-2. TAP CONTROLLER STATE DIAGRAM .............................................................................................227

33.2 INSTRUCTION REGISTER..........................................................................................................................227

TABLE 33-A. INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE................................................................228

SAMPLE/PRELOAD .........................................................................................................................................228

BYPASS .............................................................................................................................................................228

EXTEST .............................................................................................................................................................228

CLAMP..............................................................................................................................................................228

HIGHZ...............................................................................................................................................................228

IDCODE............................................................................................................................................................228

TABLE 33-B. ID CODE STRUCTURE ......................................................................................................................229

TABLE 33-C. DEVICE ID CODES ...........................................................................................................................229

33.3 TEST REGISTERS......................................................................................................................................229

33.4 BOUNDARY SCAN REGISTER ...................................................................................................................229

33.5 BYPASS REGISTER ...................................................................................................................................229

33.6 IDENTIFICATION REGISTER .....................................................................................................................229

TABLE 33-D. BOUNDARY SCAN CONTROL BITS...................................................................................................230

34. FUNCTIONAL TIMING DIAGRAMS...................................................................................................233

34.1 T1 MODE .................................................................................................................................................233

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