DS2156 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Dallas Semiconductor -> Maxim Integrated 

DS2156

3.3 Parallel Control Port Pins

Signal Name:

INT

Signal Description:

Interrupt

Signal Type:

Output

Flags host controller during conditions and events defined in the status registers. Active-low, open-drain output.

Signal Name:

TSTRST

Signal Description:

Three-State Control and Device Reset

Signal Type:

Input

A dual function pin. A 0-to-1 transition issues a hardware reset to the DS2156 register set. A reset clears all

configuration registers. Configuration register contents are set to 0. Leaving TSTRST high three-states all output

and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing.

Signal Name:

MUX

Signal Description:

Bus Operation

Signal Type:

Input

Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.

Signal Name:

AD0 to AD7

Signal Description:

Data Bus [D0 to D7] or Address/Data Bus

Signal Type:

Input/Output

In nonmultiplexed bus operation (MUX = 0), these serve as the data bus. In multiplexed bus operation (MUX = 1),

these pins serve as an 8-bit multiplexed address/data bus.

Signal Name:

A0 to A6

Signal Description:

Address Bus

Signal Type:

Input

In nonmultiplexed bus operation (MUX = 0), these serve as the address bus. In multiplexed bus operation

(MUX = 1), these pins are not used and should be connected low.

Signal Name:

BTS

Signal Description:

Bus Type Select

Signal Type:

Input

Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the

RD (DS), ALE (AS), and WR (R/W) pins.

If BTS = 1, then these pins assume the function listed in parentheses ().

Signal Name:

RD (DS)

Signal Description:

Read Input, Data Strobe

Signal Type:

Input

RD and DS are active-low signals. DS active HIGH when MUX = 1. See Bus Timing Diagrams.

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