DS2156 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Dallas Semiconductor -> Maxim Integrated 

DS2156

Signal Name:

RMSYNC

Signal Description: Receive Multiframe Sync

Signal Type:

Output

An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is

output at this pin that identifies multiframe boundaries.

Signal Name:

RDATA

Signal Description: Receive Data

Signal Type:

Output

Updated on the rising edge of RCLK with the data out of the receive-side framer.

Signal Name:

RSYSCLK

Signal Description: Receive System Clock

Signal Type:

Input

1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic store function is

enabled. Should be connected low in applications that do not use the receive-side elastic store. See Section 28 for

details on 4.096MHz and 8.192MHz operation using the IBO.

Signal Name:

RSIG

Signal Description:

Receive Signaling Output

Signal Type:

Output

Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is

disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.

Signal Name:

RLOS/LOTC

Signal Description:

Receive Loss-of-Sync/Loss-of-Transmit Clock

Signal Type:

Output

A dual function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle

high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not

been toggled for 5ms.

Signal Name:

RCL

Signal Description:

Receive Carrier Loss

Signal Type:

Output

Set high when the line interface detects a carrier loss.

Signal Name:

RSIGF

Signal Description:

Receive Signaling Freeze

Signal Type:

Output

Set high when the signaling data is frozen by either automatic or manual intervention. Used to alert downstream

equipment of the condition.

Signal Name:

BPCLK

Signal Description:

Backplane Clock

Signal Type:

Output

A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.

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