DS2156 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Dallas Semiconductor -> Maxim Integrated 

DS2156

3. PIN FUNCTION DESCRIPTION

The DS2156 has a user-selectable TDM or UTOPIA backplane. Table 3-A and Table 3-B indicate which

pins have alternate functions depending on the backplane selected. Note that even when the UTOPIA

backplane is selected, the basic TDM signals such as clock, data, and frame-sync are available for both

the transmit and receive directions.

3.1 TDM Backplane

3.1.1 Transmit Side

Signal Name:

TCLK

Signal Description: Transmit Clock

Signal Type:

Input

A 1.544MHz (T1) or a 2.048MHz (E1) primary clock. Used to clock data through the transmit-side formatter.

TCLK can be internally sourced from MCLK. This is the most flexible method and requires only a single clock

signal for both T1 or E1. If internal sourcing is used, then the TCLK pin should be connected low.

Signal Name:

TSER

Signal Description: Transmit Serial Data

Signal Type:

Input

Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.

Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.

Signal Name:

TCHCLK

Signal Description: Transmit Channel Clock

Signal Type:

Output

A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to

output a gated transmit bit clock on a per-channel basis. Synchronous with TCLK when the transmit-side elastic

store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-

to-serial conversion of channel data.

Signal Name:

TCHBLK

Signal Description: Transmit Channel Block

Signal Type:

Output

A user-programmable output that can be forced high or low during any of the channels. Synchronous with TCLK

when the transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is

enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are

used such as Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN–PRI. Also useful for locating

individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel

conditioning.

Signal Name:

TSYSCLK

Signal Description: Transmit System Clock

Signal Type:

Input

1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic

store function is enabled. Should be connected low in applications that do not use the transmit-side elastic store.

See Section 28 for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.

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