DS2156 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2156

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Dallas Semiconductor -> Maxim Integrated 

DS2156

Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In

each 125ms frame there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent

first followed by channel 1. Each channel is made up of eight bits that are numbered 1 to 8. Bit number 1

is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. The term “locked” is

used to refer to two clock signals that are phase- or frequency-locked or derived from a common clock

(i.e., a 1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).

Throughout this data sheet, the following abbreviations are used:

B8ZS

BOC

CRC

D4

ESF

FDL

FPS

Fs

Ft

HDLC

MF

SLC–96

Bipolar with 8 Zero Substitution

Bit-Oriented Code

Cyclical Redundancy Check

Superframe (12 frames per multiframe) Multiframe Structure

Extended Superframe (24 frames per multiframe) Multiframe Structure

Facility Data Link

Framing Pattern Sequence in ESF

Signaling Framing Pattern in D4

Terminal Framing Pattern in D4

High-Level Data Link Control

Multiframe

Subscriber Loop Carrier—96 Channels

12 of 262

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